From 0d74f273136627a02a5d70b4dc67b59507c3d559 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 31 Jan 2006 15:00:09 -0500
Subject: [PATCH] More changes toward making simpleCpu use new port interface.

cpu/simple/cpu.cc:
    Initialize the ports, also add Request and Packet instead of MemReq.  Initial work at ICache read in place.
cpu/simple/cpu.hh:
    Need to call the completion handler when we see a recieve.

--HG--
extra : convert_revision : a52caee6f0ceb5d9ee1e5acca63a202f5ea71359
---
 cpu/simple/cpu.cc | 36 ++++++++++++++++++++++++++----------
 cpu/simple/cpu.hh | 16 +++++-----------
 2 files changed, 31 insertions(+), 21 deletions(-)

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index a7f4fa499..d913505f1 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -115,7 +115,7 @@ SimpleCPU::CacheCompletionEvent::description()
 
 SimpleCPU::SimpleCPU(Params *p)
     : BaseCPU(p), tickEvent(this, p->width), xc(NULL),
-      cacheCompletionEvent(this)
+      cacheCompletionEvent(this), dcache_port(this), icache_port(this)
 {
     _status = Idle;
 #if FULL_SYSTEM
@@ -130,10 +130,12 @@ SimpleCPU::SimpleCPU(Params *p)
     icacheInterface = p->icache_interface;
     dcacheInterface = p->dcache_interface;
 
-    memReq = new MemReq();
-    memReq->xc = xc;
-    memReq->asid = 0;
-    memReq->data = new uint8_t[64];
+    req = new CpuRequest();
+    pkt = new Packet();
+
+    req->asid = 0;
+    pkt->req = req;
+    pkt->data = new uint8_t[64];
 
     numInst = 0;
     startNumInst = 0;
@@ -704,16 +706,20 @@ SimpleCPU::tick()
 #define IFETCH_FLAGS(pc)	0
 #endif
 
-        memReq->cmd = Read;
-        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
-                     IFETCH_FLAGS(xc->regs.pc));
+        pkt->cmd = Read;
+        req->paddr = xc->regs.pc & ~3;
+        pkt->size = sizeof(uint32_t);
 
+/*	memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
+                     IFETCH_FLAGS(xc->regs.pc));
+*/
+//NEED NEW TRANSLATION HERE
         fault = xc->translateInstReq(memReq);
 
         if (fault == No_Fault)
             fault = xc->mem->read(memReq, inst);
 
-        if (icacheInterface && fault == No_Fault) {
+/*	if (icacheInterface && fault == No_Fault) {
             memReq->completionEvent = NULL;
 
             memReq->time = curTick;
@@ -723,7 +729,7 @@ SimpleCPU::tick()
             // Ugly hack to get an event scheduled *only* if the access is
             // a miss.  We really should add first-class support for this
             // at some point.
-            if (result != MA_HIT && icacheInterface->doEvents()) {
+                if (result != MA_HIT && icacheInterface->doEvents()) {
                 memReq->completionEvent = &cacheCompletionEvent;
                 lastIcacheStall = curTick;
                 unscheduleTickEvent();
@@ -731,6 +737,16 @@ SimpleCPU::tick()
                 return;
             }
         }
+*/
+        bool success = icache_port.sendTiming(pkt);
+        if (!success)
+        {
+            //Need to wait for retry
+            lastIcacheStall = curTick;
+            unscheduleTickEvent();
+            _status = IcacheMissStall;
+            return;
+        }
     }
 
     // If we've got a valid instruction (i.e., no fault on instruction
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 0fb6235b4..ac4e1cf22 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -80,13 +80,13 @@ class SimpleCPU : public BaseCPU
       protected:
 
         virtual bool recvTiming(Packet &pkt)
-        { return cpu->recvTiming(pkt); }
+        { return cpu->processCacheCompletion(pkt); }
 
         virtual Tick recvAtomic(Packet &pkt)
-        { return cpu->recvAtomic(pkt); }
+        { return cpu->processCacheCompletion(pkt); }
 
         virtual void recvFunctional(Packet &pkt)
-        { cpu->recvFunctional(pkt); }
+        { cpu->processCacheCompletion(pkt); }
 
         virtual void recvStatusChange(Status status)
         { cpu->recvStatusChange(status); }
@@ -192,17 +192,11 @@ class SimpleCPU : public BaseCPU
     bool interval_stats;
 #endif
 
-    // L1 instruction cache
-    MemInterface *icacheInterface;
-
-    // L1 data cache
-    MemInterface *dcacheInterface;
-
     // current instruction
     MachInst inst;
 
-    // Refcounted pointer to the one memory request.
-    MemReqPtr memReq;
+    CpuRequest *req;
+    Packet *pkt;
 
     // Pointer to the sampler that is telling us to switchover.
     // Used to signal the completion of the pipe drain and schedule
-- 
2.30.2