From 0d76c5be4d21d05c5efd3ec7ba5f4f6ac6c33a49 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 15 May 2019 08:29:00 +0100 Subject: [PATCH] increase counter, experiment with longer completion times --- src/experiment/compalu.py | 2 +- src/experiment/cscore.py | 1 + src/scoreboard/fn_unit.py | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py index 2edf6587..3c97c19a 100644 --- a/src/experiment/compalu.py +++ b/src/experiment/compalu.py @@ -54,7 +54,7 @@ class ComputationUnitNoDelay(Elaboratable): m.d.comb += self.busy_o.eq(opc_l.q) # busy out with m.If(self.go_rd_i): - m.d.sync += self.counter.eq(1) + m.d.sync += self.counter.eq(2) with m.If(self.counter > 0): m.d.sync += self.counter.eq(self.counter - 1) with m.If(self.counter == 1): diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py index 8003c54f..61f7ec09 100644 --- a/src/experiment/cscore.py +++ b/src/experiment/cscore.py @@ -337,6 +337,7 @@ def scoreboard_sim(dut, alusim): yield yield yield + yield while True: issue_o = yield dut.issue_o if issue_o: diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py index af7b0ea2..d706b7f1 100644 --- a/src/scoreboard/fn_unit.py +++ b/src/scoreboard/fn_unit.py @@ -163,7 +163,7 @@ class FnUnit(Elaboratable): # readable output signal g_rd = Signal(self.reg_width, reset_less=True) ro = Signal(reset_less=True) - m.d.comb += g_rd.eq((~self.g_wr_pend_i) & self.rd_pend_o) + m.d.comb += g_rd.eq(~self.g_wr_pend_i & self.rd_pend_o) m.d.comb += ro.eq(g_rd.bool()) m.d.comb += self.readable_o.eq(ro) -- 2.30.2