From 0d9fd4eafc7327131b788c8a909202e6baa721d1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 20 Jul 2018 11:13:50 +0100 Subject: [PATCH] add pinmux cell connections --- src/bsv/bsv_lib/slow_peripherals_template.bsv | 17 ++++++++-------- src/bsv/peripheral_gen.py | 20 ++++++++++++++++--- src/bsv/pinmux_generator.py | 7 ++++--- 3 files changed, 29 insertions(+), 15 deletions(-) diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv index 1048468..026449d 100644 --- a/src/bsv/bsv_lib/slow_peripherals_template.bsv +++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv @@ -81,7 +81,7 @@ package slow_peripherals; (*synthesize*) module mkslow_peripherals#(Clock fast_clock, Reset fast_reset, Clock uart_clock, Reset uart_reset - `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif + `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_slow_peripherals); Clock sp_clock <-exposeCurrentClock; // slow peripheral clock Reset sp_reset <-exposeCurrentReset; // slow peripheral reset @@ -112,24 +112,23 @@ package slow_peripherals; /*======= Slave connections to AXI4Lite fabric =========*/ {6} `ifdef CLINT - mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))], + mkConnection (slow_fabric.v_to_slaves + [fromInteger(valueOf(CLINT_slave_num))], clint.axi4_slave); `endif `ifdef PLIC - mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))], + mkConnection (slow_fabric.v_to_slaves + [fromInteger(valueOf(Plic_slave_num))], plic.axi4_slave_plic); // `endif `ifdef AXIEXP - mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))], + mkConnection (slow_fabric.v_to_slaves + [fromInteger(valueOf(AxiExp1_slave_num))], axiexp1.axi_slave); // `endif /*========== pinmux connections ============*/ - rule connect_select_lines_pinmux;// mandatory - pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]); - pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]); - pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]); - endrule +{7} rule connect_i2c0_scl; pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out); pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en)); diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py index b269af3..20cc188 100644 --- a/src/bsv/peripheral_gen.py +++ b/src/bsv/peripheral_gen.py @@ -192,8 +192,8 @@ class gpio(PBase): return ("%s\n%s" % (ret, ret2), 2) def mkslow_peripheral(self): - return " MUX#(%(name)s) mux{0} <- mkmux();\n" + \ - " GPIO#(%(name)s) gpio{0} <- mkgpio();" % \ + return " MUX#(%(name)s) mux{0} <- mkmux();\n" + \ + " GPIO#(%(name)s) gpio{0} <- mkgpio();" % \ {'name': self.name} def mk_connection(self, count): @@ -222,6 +222,12 @@ typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif ) typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves; """ +pinmux_cellrule = """\ + rule connect_select_lines_pinmux; +{0} + endrule +""" + class CallFn(object): def __init__(self, peripheral, name): @@ -229,7 +235,7 @@ class CallFn(object): self.name = name def __call__(self, *args): - print "__call__", self.name, self.peripheral.slow, args + #print "__call__", self.name, self.peripheral.slow, args if not self.peripheral.slow: return '' return getattr(self.peripheral.slow, self.name)(*args[1:]) @@ -337,6 +343,14 @@ class PeripheralInterfaces(object): ret.append(txt) return '\n'.join(list(filter(None, ret))) + def mk_cellconn(self): + ret = [] + txt = " pinmux.mux_lines.cell{0}_mux(muxa.mux_config.mux[{0}]);" + for (name, count) in self.ifacecount: + for i in range(count): + ret.append(txt.format(i)) + ret = '\n'.join(list(filter(None, ret))) + return pinmux_cellrule.format(ret) class PFactory(object): def getcls(self, name): diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 6a41b31..e33c082 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -90,10 +90,10 @@ def pinmuxgen(pth=None, verify=True): write_bvp(bvp, p, ifaces) write_bus(bus, p, ifaces) write_instances(idef, p, ifaces) - write_slow(slow, slowt, p, ifaces) + write_slow(slow, slowt, p, ifaces, iocells) -def write_slow(slow, template, p, ifaces): +def write_slow(slow, template, p, ifaces, iocells): """ write out the slow_peripherals.bsv file. joins all the peripherals together into one AXI Lite interface """ @@ -106,9 +106,10 @@ def write_slow(slow, template, p, ifaces): fnaddrmap = ifaces.axi_addr_map() mkslow = ifaces.mkslow_peripheral() mkcon = ifaces.mk_connection() + mkcellcon = iocells.mk_cellconn() with open(slow, "w") as bsv_file: bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl, - fnaddrmap, mkslow, mkcon)) + fnaddrmap, mkslow, mkcon, mkcellcon)) def write_bus(bus, p, ifaces): -- 2.30.2