From 0da94fa19c70621339a7f934bd21925da839b10a Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 18 Jun 2018 16:02:14 -0400 Subject: [PATCH] radeonsi: don't enable DCC statistics gathering for small surfaces --- src/gallium/drivers/radeonsi/si_clear.c | 30 +++++++++++++------------ 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 6313f904b41..8a3398c70c0 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -432,20 +432,6 @@ static void si_do_fast_color_clear(struct si_context *sctx, !sctx->screen->info.htile_cmask_support_1d_tiling) continue; - /* Fast clear is the most appropriate place to enable DCC for - * displayable surfaces. - */ - vi_separate_dcc_try_enable(sctx, tex); - - /* RB+ isn't supported with a CMASK clear only on Stoney, - * so all clears are considered to be hypothetically slow - * clears, which is weighed when determining whether to - * enable separate DCC. - */ - if (tex->dcc_gather_statistics && - sctx->family == CHIP_STONEY) - tex->num_slow_clears++; - bool need_decompress_pass = false; /* Use a slow clear for small surfaces where the cost of @@ -458,6 +444,22 @@ static void si_do_fast_color_clear(struct si_context *sctx, tex->buffer.b.b.width0 * tex->buffer.b.b.height0 <= 512 * 512; + /* Fast clear is the most appropriate place to enable DCC for + * displayable surfaces. + */ + if (!too_small) { + vi_separate_dcc_try_enable(sctx, tex); + + /* RB+ isn't supported with a CMASK clear only on Stoney, + * so all clears are considered to be hypothetically slow + * clears, which is weighed when determining whether to + * enable separate DCC. + */ + if (tex->dcc_gather_statistics && + sctx->family == CHIP_STONEY) + tex->num_slow_clears++; + } + /* Try to clear DCC first, otherwise try CMASK. */ if (vi_dcc_enabled(tex, 0)) { uint32_t reset_value; -- 2.30.2