From 0daff5e0c87a619093f4718c0ec212b1b461bfde Mon Sep 17 00:00:00 2001 From: Oleg Endo Date: Thu, 21 May 2015 12:36:35 +0000 Subject: [PATCH] re PR target/54236 ([SH] Improve addc and subc insn utilization) gcc/ PR target/54236 * config/sh/sh.md (*round_int_even): Reject pattern if operands[0] and operands[1] are the same. gcc/testsuite/ PR target/54236 * gcc.target/sh/pr54236-2.c: Fix typo in comment. From-SVN: r223479 --- gcc/ChangeLog | 6 ++++++ gcc/config/sh/sh.md | 3 ++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/sh/pr54236-2.c | 2 +- 4 files changed, 14 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 550d98c30eb..9218257629f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-05-21 Oleg Endo + + PR target/54236 + * config/sh/sh.md (*round_int_even): Reject pattern if operands[0] and + operands[1] are the same. + 2015-05-21 Ilya Enkovich PR middle-end/66221 diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 3b669928a20..2d95b9c1e22 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -2011,7 +2011,8 @@ (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)) (const_int -2)))] - "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p ()" + "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p () + && !reg_overlap_mentioned_p (operands[0], operands[1])" "#" "&& 1" [(set (match_dup 0) (const_int -2)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 81f6779da05..2cd1577e067 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-05-21 Oleg Endo + + PR target/54236 + * gcc.target/sh/pr54236-2.c: Fix typo in comment. + 2015-05-21 Ramana Radhakrishnan PR target/65937 diff --git a/gcc/testsuite/gcc.target/sh/pr54236-2.c b/gcc/testsuite/gcc.target/sh/pr54236-2.c index b94c2c0a5e2..c72afb92957 100644 --- a/gcc/testsuite/gcc.target/sh/pr54236-2.c +++ b/gcc/testsuite/gcc.target/sh/pr54236-2.c @@ -133,7 +133,7 @@ int test_016 (int a, int b, int c, int d) { // non-SH2A: 1x add #1, 1x mov #-2, 1x and - // SH2A: 1x add #1, 1x blcr #0 + // SH2A: 1x add #1, 1x bclr #0 return a + (a & 1); } -- 2.30.2