From 0db4455c1f2f3cff76f3c15081c020c0fb229a47 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 30 Dec 2019 16:34:22 -0800 Subject: [PATCH] intel/fs/gen6: Constrain barycentric source of LINTERP during bank conflict mitigation. This avoids regressions on SNB due to the bank conflict mitigation pass moving a VGRF-allocated barycentric vector to a misaligned location, which would prevent the PLN instruction from being used. Reviewed-by: Kenneth Graunke --- src/intel/compiler/brw_fs_bank_conflicts.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/intel/compiler/brw_fs_bank_conflicts.cpp b/src/intel/compiler/brw_fs_bank_conflicts.cpp index e908d0e38fc..f10caf249d0 100644 --- a/src/intel/compiler/brw_fs_bank_conflicts.cpp +++ b/src/intel/compiler/brw_fs_bank_conflicts.cpp @@ -567,6 +567,14 @@ namespace { constrained[p.atom_of_reg(reg_of(inst->src[i]))] = true; } + /* Preserve the original allocation of VGRFs used by the barycentric + * source of the LINTERP instruction on Gen6, since pair-aligned + * barycentrics allow the PLN instruction to be used. + */ + if (v->devinfo->has_pln && v->devinfo->gen <= 6 && + inst->opcode == FS_OPCODE_LINTERP) + constrained[p.atom_of_reg(reg_of(inst->src[0]))] = true; + /* The location of the Gen7 MRF hack registers is hard-coded in the * rest of the compiler back-end. Don't attempt to move them around. */ -- 2.30.2