From 0dd75e288467ee55dc91050f68895570e9659645 Mon Sep 17 00:00:00 2001 From: Josh Vanderhoof Date: Wed, 3 Nov 1999 18:50:44 +0000 Subject: [PATCH] swap operand order for Intel style REGOFF --- src/mesa/x86/assyntax.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mesa/x86/assyntax.h b/src/mesa/x86/assyntax.h index 0a8c1bda978..1d476ce49b0 100644 --- a/src/mesa/x86/assyntax.h +++ b/src/mesa/x86/assyntax.h @@ -974,12 +974,12 @@ #define B_REGIND(a) BYTE_PTR [a] /* Register b indirect plus displacement a */ -#define P_REGOFF(a, b) [a + b] -#define X_REGOFF(a, b) TBYTE_PTR [a + b] -#define D_REGOFF(a, b) QWORD_PTR [a + b] -#define L_REGOFF(a, b) DWORD_PTR [a + b] -#define W_REGOFF(a, b) WORD_PTR [a + b] -#define B_REGOFF(a, b) BYTE_PTR [a + b] +#define P_REGOFF(a, b) [b + a] +#define X_REGOFF(a, b) TBYTE_PTR [b + a] +#define D_REGOFF(a, b) QWORD_PTR [b + a] +#define L_REGOFF(a, b) DWORD_PTR [b + a] +#define W_REGOFF(a, b) WORD_PTR [b + a] +#define B_REGOFF(a, b) BYTE_PTR [b + a] /* Reg indirect Base + Index + Displacement - this is mainly for 16-bit mode * which has no scaling -- 2.30.2