From 0df2753ad21175d8914a8c2ca512cf79246c10fd Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 5 Sep 2012 14:35:21 -0400 Subject: [PATCH] radeon/llvm: Add register encoding for VCC MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp index 438d2acf989..ca4b579dcce 100644 --- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp @@ -280,6 +280,7 @@ unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const { unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const { switch (reg) { + case AMDGPU::VCC: return 106; case AMDGPU::M0: return 124; case AMDGPU::EXEC: return 126; case AMDGPU::EXEC_LO: return 126; -- 2.30.2