From 0dfca49e68ea8e9500b485d993f3e91a8d8e2d78 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Feb 2015 10:53:51 +0100 Subject: [PATCH] litesata: move file and modify import to misoclib.mem.litesata --- misoclib/mem/.gitignore | 3 --- misoclib/mem/build/.keep_me | 0 misoclib/mem/{ => litesata}/LICENSE | 0 misoclib/mem/{ => litesata}/README | 0 misoclib/mem/litesata/__init__.py | 8 ++++---- misoclib/mem/litesata/core/__init__.py | 8 ++++---- misoclib/mem/litesata/core/command/__init__.py | 2 +- misoclib/mem/litesata/core/link/__init__.py | 8 ++++---- misoclib/mem/litesata/core/link/cont.py | 4 ++-- misoclib/mem/litesata/core/link/crc.py | 2 +- misoclib/mem/litesata/core/link/scrambler.py | 2 +- misoclib/mem/litesata/core/transport/__init__.py | 2 +- misoclib/mem/{ => litesata}/doc/.gitignore | 0 misoclib/mem/{ => litesata}/doc/Makefile | 0 misoclib/mem/{ => litesata}/doc/make.bat | 0 .../doc/source/_static/LiteSATA_logo_full.png | Bin .../doc/source/_static/LiteSATA_logo_full.svg | 0 .../enjoydigital_sphinx_rtd_theme/__init__.py | 0 .../enjoydigital_sphinx_rtd_theme/breadcrumbs.html | 0 .../enjoydigital_sphinx_rtd_theme/footer.html | 0 .../enjoydigital_sphinx_rtd_theme/layout.html | 0 .../enjoydigital_sphinx_rtd_theme/layout_old.html | 0 .../enjoydigital_sphinx_rtd_theme/search.html | 0 .../enjoydigital_sphinx_rtd_theme/searchbox.html | 0 .../static/css/badge_only.css | 0 .../static/css/theme - prior to centering.css | 0 .../static/css/theme.css | 0 .../static/fonts/fontawesome-webfont.eot | Bin .../static/fonts/fontawesome-webfont.svg | 0 .../static/fonts/fontawesome-webfont.ttf | Bin .../static/fonts/fontawesome-webfont.woff | Bin .../static/js/theme.js | 0 .../enjoydigital_sphinx_rtd_theme/theme.conf | 0 .../enjoydigital_sphinx_rtd_theme/versions.html | 0 misoclib/mem/{ => litesata}/doc/source/conf.py | 0 .../{ => litesata}/doc/source/docs/core/index.rst | 0 .../doc/source/docs/frontend/index.rst | 0 .../doc/source/docs/getting_started/FAQ.rst | 0 .../doc/source/docs/getting_started/bug_reports.rst | 0 .../doc/source/docs/getting_started/downloads.rst | 0 .../doc/source/docs/getting_started/index.rst | 0 .../mem/{ => litesata}/doc/source/docs/index.rst | 0 .../{ => litesata}/doc/source/docs/intro/about.rst | 0 .../doc/source/docs/intro/community.rst | 0 .../{ => litesata}/doc/source/docs/intro/index.rst | 0 .../doc/source/docs/intro/license.rst | 0 .../doc/source/docs/intro/release_notes.rst | 0 .../source/docs/intro/talks_and_publications.rst | 0 .../{ => litesata}/doc/source/docs/phy/index.rst | 0 .../doc/source/docs/simulation/index.rst | 0 .../source/docs/specification/byte_word_dword.png | Bin .../doc/source/docs/specification/crc.png | Bin .../doc/source/docs/specification/index.rst | 0 .../doc/source/docs/specification/oob_sequence.png | Bin .../doc/source/docs/specification/oob_signals.png | Bin .../doc/source/docs/specification/sata_layers.png | Bin .../doc/source/docs/specification/scrambler.png | Bin .../{ => litesata}/doc/source/docs/test/index.rst | 0 .../{ => litesata}/doc/source/home_page_layout.html | 0 misoclib/mem/{ => litesata}/doc/source/index.rst | 0 misoclib/mem/{ => litesata/example_designs}/make.py | 5 +++-- .../example_designs}/platforms/kc705.py | 0 .../example_designs}/platforms/verilog_backend.py | 0 .../example_designs}/targets/__init__.py | 0 .../{ => litesata/example_designs}/targets/bist.py | 8 ++++---- .../{ => litesata/example_designs}/targets/core.py | 6 +++--- .../mem/{ => litesata/example_designs}/test/bist.py | 0 .../{ => litesata/example_designs}/test/config.py | 0 .../{ => litesata/example_designs}/test/test_la.py | 0 .../example_designs}/test/test_regs.py | 0 .../{ => litesata/example_designs}/test/tools.py | 0 misoclib/mem/litesata/frontend/__init__.py | 8 ++++---- misoclib/mem/litesata/frontend/arbiter.py | 4 ++-- misoclib/mem/litesata/frontend/bist.py | 4 ++-- misoclib/mem/litesata/frontend/common.py | 2 +- misoclib/mem/litesata/frontend/crossbar.py | 6 +++--- misoclib/mem/{ => litesata}/icarus_workaround.patch | 0 misoclib/mem/{ => litesata}/litesata-version.txt | 0 misoclib/mem/litesata/phy/__init__.py | 10 +++++----- misoclib/mem/litesata/phy/ctrl.py | 2 +- misoclib/mem/litesata/phy/datapath.py | 2 +- misoclib/mem/litesata/phy/k7/crg.py | 2 +- misoclib/mem/litesata/phy/k7/trx.py | 2 +- misoclib/mem/{ => litesata}/setup.py | 0 misoclib/mem/litesata/test/bist_tb.py | 10 +++++----- misoclib/mem/litesata/test/command_tb.py | 8 ++++---- misoclib/mem/litesata/test/common.py | 2 +- misoclib/mem/litesata/test/cont_tb.py | 6 +++--- misoclib/mem/litesata/test/crc_tb.py | 6 +++--- misoclib/mem/litesata/test/hdd.py | 4 ++-- misoclib/mem/litesata/test/link_tb.py | 8 ++++---- misoclib/mem/litesata/test/phy_datapath_tb.py | 6 +++--- misoclib/mem/litesata/test/scrambler_tb.py | 6 +++--- 93 files changed, 77 insertions(+), 79 deletions(-) delete mode 100644 misoclib/mem/.gitignore delete mode 100644 misoclib/mem/build/.keep_me rename misoclib/mem/{ => litesata}/LICENSE (100%) rename misoclib/mem/{ => litesata}/README (100%) rename misoclib/mem/{ => litesata}/doc/.gitignore (100%) rename misoclib/mem/{ => litesata}/doc/Makefile (100%) rename misoclib/mem/{ => litesata}/doc/make.bat (100%) rename misoclib/mem/{ => litesata}/doc/source/_static/LiteSATA_logo_full.png (100%) rename misoclib/mem/{ => litesata}/doc/source/_static/LiteSATA_logo_full.svg (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/__init__.py (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/breadcrumbs.html (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/footer.html (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout.html (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout_old.html (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/search.html (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/searchbox.html (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/css/badge_only.css (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/css/theme - prior to centering.css (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/css/theme.css (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/fonts/fontawesome-webfont.eot (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/fonts/fontawesome-webfont.svg (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/fonts/fontawesome-webfont.ttf (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/fonts/fontawesome-webfont.woff (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/static/js/theme.js (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/theme.conf (100%) rename misoclib/mem/{ => litesata}/doc/source/_themes/enjoydigital_sphinx_rtd_theme/versions.html (100%) rename misoclib/mem/{ => litesata}/doc/source/conf.py (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/core/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/frontend/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/getting_started/FAQ.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/getting_started/bug_reports.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/getting_started/downloads.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/getting_started/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/intro/about.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/intro/community.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/intro/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/intro/license.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/intro/release_notes.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/intro/talks_and_publications.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/phy/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/simulation/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/specification/byte_word_dword.png (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/specification/crc.png (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/specification/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/specification/oob_sequence.png (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/specification/oob_signals.png (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/specification/sata_layers.png (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/specification/scrambler.png (100%) rename misoclib/mem/{ => litesata}/doc/source/docs/test/index.rst (100%) rename misoclib/mem/{ => litesata}/doc/source/home_page_layout.html (100%) rename misoclib/mem/{ => litesata}/doc/source/index.rst (100%) rename misoclib/mem/{ => litesata/example_designs}/make.py (97%) rename misoclib/mem/{ => litesata/example_designs}/platforms/kc705.py (100%) rename misoclib/mem/{ => litesata/example_designs}/platforms/verilog_backend.py (100%) rename misoclib/mem/{ => litesata/example_designs}/targets/__init__.py (100%) rename misoclib/mem/{ => litesata/example_designs}/targets/bist.py (97%) rename misoclib/mem/{ => litesata/example_designs}/targets/core.py (92%) rename misoclib/mem/{ => litesata/example_designs}/test/bist.py (100%) rename misoclib/mem/{ => litesata/example_designs}/test/config.py (100%) rename misoclib/mem/{ => litesata/example_designs}/test/test_la.py (100%) rename misoclib/mem/{ => litesata/example_designs}/test/test_regs.py (100%) rename misoclib/mem/{ => litesata/example_designs}/test/tools.py (100%) rename misoclib/mem/{ => litesata}/icarus_workaround.patch (100%) rename misoclib/mem/{ => litesata}/litesata-version.txt (100%) rename misoclib/mem/{ => litesata}/setup.py (100%) diff --git a/misoclib/mem/.gitignore b/misoclib/mem/.gitignore deleted file mode 100644 index 065c5521..00000000 --- a/misoclib/mem/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -__pycache__ -*.pyc -*.vcd diff --git a/misoclib/mem/build/.keep_me b/misoclib/mem/build/.keep_me deleted file mode 100644 index e69de29b..00000000 diff --git a/misoclib/mem/LICENSE b/misoclib/mem/litesata/LICENSE similarity index 100% rename from misoclib/mem/LICENSE rename to misoclib/mem/litesata/LICENSE diff --git a/misoclib/mem/README b/misoclib/mem/litesata/README similarity index 100% rename from misoclib/mem/README rename to misoclib/mem/litesata/README diff --git a/misoclib/mem/litesata/__init__.py b/misoclib/mem/litesata/__init__.py index 124e0281..dd93affd 100644 --- a/misoclib/mem/litesata/__init__.py +++ b/misoclib/mem/litesata/__init__.py @@ -1,7 +1,7 @@ -from litesata.common import * -from litesata.phy import * -from litesata.core import * -from litesata.frontend import * +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.phy import * +from misoclib.mem.litesata.core import * +from misoclib.mem.litesata.frontend import * from migen.bank.description import * diff --git a/misoclib/mem/litesata/core/__init__.py b/misoclib/mem/litesata/core/__init__.py index e318c5f2..9ca40190 100644 --- a/misoclib/mem/litesata/core/__init__.py +++ b/misoclib/mem/litesata/core/__init__.py @@ -1,7 +1,7 @@ -from litesata.common import * -from litesata.core.link import LiteSATALink -from litesata.core.transport import LiteSATATransport -from litesata.core.command import LiteSATACommand +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link import LiteSATALink +from misoclib.mem.litesata.core.transport import LiteSATATransport +from misoclib.mem.litesata.core.command import LiteSATACommand class LiteSATACore(Module): def __init__(self, phy, buffer_depth): diff --git a/misoclib/mem/litesata/core/command/__init__.py b/misoclib/mem/litesata/core/command/__init__.py index 0229befa..d3c5d0da 100644 --- a/misoclib/mem/litesata/core/command/__init__.py +++ b/misoclib/mem/litesata/core/command/__init__.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * tx_to_rx = [ ("write", 1), diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py index 2be40541..74e3d611 100644 --- a/misoclib/mem/litesata/core/link/__init__.py +++ b/misoclib/mem/litesata/core/link/__init__.py @@ -1,7 +1,7 @@ -from litesata.common import * -from litesata.core.link.crc import LiteSATACRCInserter, LiteSATACRCChecker -from litesata.core.link.scrambler import LiteSATAScrambler -from litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link.crc import LiteSATACRCInserter, LiteSATACRCChecker +from misoclib.mem.litesata.core.link.scrambler import LiteSATAScrambler +from misoclib.mem.litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover from_rx = [ ("idle", 1), diff --git a/misoclib/mem/litesata/core/link/cont.py b/misoclib/mem/litesata/core/link/cont.py index 0984374b..f72affce 100644 --- a/misoclib/mem/litesata/core/link/cont.py +++ b/misoclib/mem/litesata/core/link/cont.py @@ -1,5 +1,5 @@ -from litesata.common import * -from litesata.core.link.scrambler import Scrambler +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link.scrambler import Scrambler class LiteSATACONTInserter(Module): def __init__(self, description): diff --git a/misoclib/mem/litesata/core/link/crc.py b/misoclib/mem/litesata/core/link/crc.py index d73b047d..7cb6e714 100644 --- a/misoclib/mem/litesata/core/link/crc.py +++ b/misoclib/mem/litesata/core/link/crc.py @@ -1,5 +1,5 @@ from collections import OrderedDict -from litesata.common import * +from misoclib.mem.litesata.common import * from migen.actorlib.crc import CRCInserter, CRCChecker diff --git a/misoclib/mem/litesata/core/link/scrambler.py b/misoclib/mem/litesata/core/link/scrambler.py index 99ad98ce..e0f9e4a0 100644 --- a/misoclib/mem/litesata/core/link/scrambler.py +++ b/misoclib/mem/litesata/core/link/scrambler.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * @DecorateModule(InsertCE) class Scrambler(Module): diff --git a/misoclib/mem/litesata/core/transport/__init__.py b/misoclib/mem/litesata/core/transport/__init__.py index a066fb7c..b8015b81 100644 --- a/misoclib/mem/litesata/core/transport/__init__.py +++ b/misoclib/mem/litesata/core/transport/__init__.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * def _get_item(obj, name, width): if "_lsb" in name: diff --git a/misoclib/mem/doc/.gitignore b/misoclib/mem/litesata/doc/.gitignore similarity index 100% rename from misoclib/mem/doc/.gitignore rename to misoclib/mem/litesata/doc/.gitignore diff --git a/misoclib/mem/doc/Makefile b/misoclib/mem/litesata/doc/Makefile similarity index 100% rename from misoclib/mem/doc/Makefile rename to misoclib/mem/litesata/doc/Makefile diff --git a/misoclib/mem/doc/make.bat b/misoclib/mem/litesata/doc/make.bat similarity index 100% rename from misoclib/mem/doc/make.bat rename to misoclib/mem/litesata/doc/make.bat diff --git a/misoclib/mem/doc/source/_static/LiteSATA_logo_full.png b/misoclib/mem/litesata/doc/source/_static/LiteSATA_logo_full.png similarity index 100% rename from misoclib/mem/doc/source/_static/LiteSATA_logo_full.png rename to misoclib/mem/litesata/doc/source/_static/LiteSATA_logo_full.png diff --git a/misoclib/mem/doc/source/_static/LiteSATA_logo_full.svg b/misoclib/mem/litesata/doc/source/_static/LiteSATA_logo_full.svg similarity index 100% rename from misoclib/mem/doc/source/_static/LiteSATA_logo_full.svg rename to misoclib/mem/litesata/doc/source/_static/LiteSATA_logo_full.svg diff --git a/misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/__init__.py b/misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/__init__.py similarity index 100% rename from misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/__init__.py rename to misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/__init__.py diff --git a/misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/breadcrumbs.html b/misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/breadcrumbs.html similarity index 100% rename from misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/breadcrumbs.html rename to misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/breadcrumbs.html diff --git a/misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/footer.html b/misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/footer.html similarity index 100% rename from misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/footer.html rename to misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/footer.html diff --git a/misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout.html b/misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout.html similarity index 100% rename from misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout.html rename to misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout.html diff --git a/misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout_old.html b/misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout_old.html similarity index 100% rename from misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout_old.html rename to misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/layout_old.html diff --git a/misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/search.html b/misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/search.html similarity index 100% rename from misoclib/mem/doc/source/_themes/enjoydigital_sphinx_rtd_theme/search.html rename to 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b/misoclib/mem/litesata/doc/source/home_page_layout.html similarity index 100% rename from misoclib/mem/doc/source/home_page_layout.html rename to misoclib/mem/litesata/doc/source/home_page_layout.html diff --git a/misoclib/mem/doc/source/index.rst b/misoclib/mem/litesata/doc/source/index.rst similarity index 100% rename from misoclib/mem/doc/source/index.rst rename to misoclib/mem/litesata/doc/source/index.rst diff --git a/misoclib/mem/make.py b/misoclib/mem/litesata/example_designs/make.py similarity index 97% rename from misoclib/mem/make.py rename to misoclib/mem/litesata/example_designs/make.py index 3ee40fd0..820b872f 100644 --- a/misoclib/mem/make.py +++ b/misoclib/mem/litesata/example_designs/make.py @@ -8,9 +8,10 @@ from migen.fhdl import verilog, edif from migen.fhdl.structure import _Fragment from migen.bank.description import CSRStatus from mibuild import tools -from mibuild.xilinx_common import * +from mibuild.xilinx.common import * -from litesata.common import * +sys.path.append("../../../../") # Temporary +from misoclib.mem.litesata.common import * def get_csr_csv(regions): r = "" diff --git a/misoclib/mem/platforms/kc705.py b/misoclib/mem/litesata/example_designs/platforms/kc705.py similarity index 100% rename from misoclib/mem/platforms/kc705.py rename to misoclib/mem/litesata/example_designs/platforms/kc705.py diff --git a/misoclib/mem/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py similarity index 100% rename from misoclib/mem/platforms/verilog_backend.py rename to misoclib/mem/litesata/example_designs/platforms/verilog_backend.py diff --git a/misoclib/mem/targets/__init__.py b/misoclib/mem/litesata/example_designs/targets/__init__.py similarity index 100% rename from misoclib/mem/targets/__init__.py rename to misoclib/mem/litesata/example_designs/targets/__init__.py diff --git a/misoclib/mem/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py similarity index 97% rename from misoclib/mem/targets/bist.py rename to misoclib/mem/litesata/example_designs/targets/bist.py index b19d713c..2a8285a1 100644 --- a/misoclib/mem/targets/bist.py +++ b/misoclib/mem/litesata/example_designs/targets/bist.py @@ -1,6 +1,6 @@ import os -from litesata.common import * +from misoclib.mem.litesata.common import * from migen.bank import csrgen from migen.bus import wishbone, csr from migen.bus import wishbone2csr @@ -15,9 +15,9 @@ from litescope.bridge.uart2wb import LiteScopeUART2WB from litescope.frontend.la import LiteScopeLA from litescope.core.port import LiteScopeTerm -from litesata.common import * -from litesata.phy import LiteSATAPHY -from litesata import LiteSATA +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.phy import LiteSATAPHY +from misoclib.mem.litesata import LiteSATA class _CRG(Module): def __init__(self, platform): diff --git a/misoclib/mem/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py similarity index 92% rename from misoclib/mem/targets/core.py rename to misoclib/mem/litesata/example_designs/targets/core.py index 843406f5..e92aa330 100644 --- a/misoclib/mem/targets/core.py +++ b/misoclib/mem/litesata/example_designs/targets/core.py @@ -2,9 +2,9 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from targets import * -from litesata.common import * -from litesata.phy import LiteSATAPHY -from litesata import LiteSATA +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.phy import LiteSATAPHY +from misoclib.mem.litesata import LiteSATA class LiteSATACore(Module): default_platform = "verilog_backend" diff --git a/misoclib/mem/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py similarity index 100% rename from misoclib/mem/test/bist.py rename to misoclib/mem/litesata/example_designs/test/bist.py diff --git a/misoclib/mem/test/config.py b/misoclib/mem/litesata/example_designs/test/config.py similarity index 100% rename from misoclib/mem/test/config.py rename to misoclib/mem/litesata/example_designs/test/config.py diff --git a/misoclib/mem/test/test_la.py b/misoclib/mem/litesata/example_designs/test/test_la.py similarity index 100% rename from misoclib/mem/test/test_la.py rename to misoclib/mem/litesata/example_designs/test/test_la.py diff --git a/misoclib/mem/test/test_regs.py b/misoclib/mem/litesata/example_designs/test/test_regs.py similarity index 100% rename from misoclib/mem/test/test_regs.py rename to misoclib/mem/litesata/example_designs/test/test_regs.py diff --git a/misoclib/mem/test/tools.py b/misoclib/mem/litesata/example_designs/test/tools.py similarity index 100% rename from misoclib/mem/test/tools.py rename to misoclib/mem/litesata/example_designs/test/tools.py diff --git a/misoclib/mem/litesata/frontend/__init__.py b/misoclib/mem/litesata/frontend/__init__.py index 63785161..76102f2c 100644 --- a/misoclib/mem/litesata/frontend/__init__.py +++ b/misoclib/mem/litesata/frontend/__init__.py @@ -1,4 +1,4 @@ -from litesata.common import * -from litesata.frontend.crossbar import LiteSATACrossbar -from litesata.frontend.arbiter import LiteSATAArbiter -from litesata.frontend.bist import LiteSATABIST +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar +from misoclib.mem.litesata.frontend.arbiter import LiteSATAArbiter +from misoclib.mem.litesata.frontend.bist import LiteSATABIST diff --git a/misoclib/mem/litesata/frontend/arbiter.py b/misoclib/mem/litesata/frontend/arbiter.py index 64bedf29..ded478b3 100644 --- a/misoclib/mem/litesata/frontend/arbiter.py +++ b/misoclib/mem/litesata/frontend/arbiter.py @@ -1,5 +1,5 @@ -from litesata.common import * -from litesata.frontend.common import * +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.frontend.common import * from migen.genlib.roundrobin import * diff --git a/misoclib/mem/litesata/frontend/bist.py b/misoclib/mem/litesata/frontend/bist.py index cd405822..f9516095 100644 --- a/misoclib/mem/litesata/frontend/bist.py +++ b/misoclib/mem/litesata/frontend/bist.py @@ -1,5 +1,5 @@ -from litesata.common import * -from litesata.core.link.scrambler import Scrambler +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link.scrambler import Scrambler from migen.fhdl.decorators import ModuleDecorator from migen.bank.description import * diff --git a/misoclib/mem/litesata/frontend/common.py b/misoclib/mem/litesata/frontend/common.py index c389aa89..de33ee0e 100644 --- a/misoclib/mem/litesata/frontend/common.py +++ b/misoclib/mem/litesata/frontend/common.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * class LiteSATAMasterPort: def __init__(self, dw): diff --git a/misoclib/mem/litesata/frontend/crossbar.py b/misoclib/mem/litesata/frontend/crossbar.py index 22170449..2300af2c 100644 --- a/misoclib/mem/litesata/frontend/crossbar.py +++ b/misoclib/mem/litesata/frontend/crossbar.py @@ -1,6 +1,6 @@ -from litesata.common import * -from litesata.frontend.common import * -from litesata.frontend.arbiter import LiteSATAArbiter +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.frontend.common import * +from misoclib.mem.litesata.frontend.arbiter import LiteSATAArbiter class LiteSATACrossbar(Module): def __init__(self, core): diff --git a/misoclib/mem/icarus_workaround.patch b/misoclib/mem/litesata/icarus_workaround.patch similarity index 100% rename from misoclib/mem/icarus_workaround.patch rename to misoclib/mem/litesata/icarus_workaround.patch diff --git a/misoclib/mem/litesata-version.txt b/misoclib/mem/litesata/litesata-version.txt similarity index 100% rename from misoclib/mem/litesata-version.txt rename to misoclib/mem/litesata/litesata-version.txt diff --git a/misoclib/mem/litesata/phy/__init__.py b/misoclib/mem/litesata/phy/__init__.py index 7af74b2d..f17a3696 100644 --- a/misoclib/mem/litesata/phy/__init__.py +++ b/misoclib/mem/litesata/phy/__init__.py @@ -1,6 +1,6 @@ -from litesata.common import * -from litesata.phy.ctrl import * -from litesata.phy.datapath import * +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.phy.ctrl import * +from misoclib.mem.litesata.phy.datapath import * class LiteSATAPHY(Module): def __init__(self, device, pads, revision, clk_freq): @@ -8,8 +8,8 @@ class LiteSATAPHY(Module): self.revision = revision # Transceiver / Clocks if device[:3] == "xc7": # Kintex 7 - from litesata.phy.k7.trx import K7LiteSATAPHYTRX - from litesata.phy.k7.crg import K7LiteSATAPHYCRG + from misoclib.mem.litesata.phy.k7.trx import K7LiteSATAPHYTRX + from misoclib.mem.litesata.phy.k7.crg import K7LiteSATAPHYCRG self.submodules.trx = K7LiteSATAPHYTRX(pads, revision) self.submodules.crg = K7LiteSATAPHYCRG(pads, self.trx, revision, clk_freq) else: diff --git a/misoclib/mem/litesata/phy/ctrl.py b/misoclib/mem/litesata/phy/ctrl.py index fc48a65c..d09253f6 100644 --- a/misoclib/mem/litesata/phy/ctrl.py +++ b/misoclib/mem/litesata/phy/ctrl.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * def us(t, clk_freq): clk_period_us = 1000000/clk_freq diff --git a/misoclib/mem/litesata/phy/datapath.py b/misoclib/mem/litesata/phy/datapath.py index d9390472..71bc4f94 100644 --- a/misoclib/mem/litesata/phy/datapath.py +++ b/misoclib/mem/litesata/phy/datapath.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * class LiteSATAPHYDatapathRX(Module): def __init__(self): diff --git a/misoclib/mem/litesata/phy/k7/crg.py b/misoclib/mem/litesata/phy/k7/crg.py index 02592cf0..73bbf8ab 100644 --- a/misoclib/mem/litesata/phy/k7/crg.py +++ b/misoclib/mem/litesata/phy/k7/crg.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * class K7LiteSATAPHYCRG(Module): def __init__(self, pads, gtx, revision, clk_freq): diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py index 5e0713df..fccaa20d 100644 --- a/misoclib/mem/litesata/phy/k7/trx.py +++ b/misoclib/mem/litesata/phy/k7/trx.py @@ -1,4 +1,4 @@ -from litesata.common import * +from misoclib.mem.litesata.common import * def ones(width): return 2**width-1 diff --git a/misoclib/mem/setup.py b/misoclib/mem/litesata/setup.py similarity index 100% rename from misoclib/mem/setup.py rename to misoclib/mem/litesata/setup.py diff --git a/misoclib/mem/litesata/test/bist_tb.py b/misoclib/mem/litesata/test/bist_tb.py index 483ffb7d..c007bb38 100644 --- a/misoclib/mem/litesata/test/bist_tb.py +++ b/misoclib/mem/litesata/test/bist_tb.py @@ -1,9 +1,9 @@ -from litesata.common import * -from litesata import LiteSATA -from litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata import LiteSATA +from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker -from litesata.test.hdd import * -from litesata.test.common import * +from misoclib.mem.litesata.test.hdd import * +from misoclib.mem.litesata.test.common import * class TB(Module): def __init__(self): diff --git a/misoclib/mem/litesata/test/command_tb.py b/misoclib/mem/litesata/test/command_tb.py index 2bcc820e..29f7d2bd 100644 --- a/misoclib/mem/litesata/test/command_tb.py +++ b/misoclib/mem/litesata/test/command_tb.py @@ -1,8 +1,8 @@ -from litesata.common import * -from litesata.core import LiteSATACore +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core import LiteSATACore -from litesata.test.hdd import * -from litesata.test.common import * +from misoclib.mem.litesata.test.hdd import * +from misoclib.mem.litesata.test.common import * class CommandTXPacket(list): def __init__(self, write=0, read=0, sector=0, count=0, data=[]): diff --git a/misoclib/mem/litesata/test/common.py b/misoclib/mem/litesata/test/common.py index ec8da980..8a91209e 100644 --- a/misoclib/mem/litesata/test/common.py +++ b/misoclib/mem/litesata/test/common.py @@ -2,7 +2,7 @@ import random, copy from migen.sim.generic import run_simulation -from litesata.common import * +from misoclib.mem.litesata.common import * def seed_to_data(seed, random=True): if random: diff --git a/misoclib/mem/litesata/test/cont_tb.py b/misoclib/mem/litesata/test/cont_tb.py index cdbb9bf2..5a71ed53 100644 --- a/misoclib/mem/litesata/test/cont_tb.py +++ b/misoclib/mem/litesata/test/cont_tb.py @@ -1,7 +1,7 @@ -from litesata.common import * -from litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover -from litesata.test.common import * +from misoclib.mem.litesata.test.common import * class ContPacket(list): def __init__(self, data=[]): diff --git a/misoclib/mem/litesata/test/crc_tb.py b/misoclib/mem/litesata/test/crc_tb.py index 3799f755..2d93b0b8 100644 --- a/misoclib/mem/litesata/test/crc_tb.py +++ b/misoclib/mem/litesata/test/crc_tb.py @@ -1,9 +1,9 @@ import subprocess -from litesata.common import * -from litesata.core.link.crc import * +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link.crc import * -from litesata.test.common import * +from misoclib.mem.litesata.test.common import * class TB(Module): def __init__(self, length, random): diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py index cab36265..fa1eed9d 100644 --- a/misoclib/mem/litesata/test/hdd.py +++ b/misoclib/mem/litesata/test/hdd.py @@ -1,8 +1,8 @@ import subprocess import math -from litesata.common import * -from litesata.test.common import * +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.test.common import * def print_with_prefix(s, prefix=""): if not isinstance(s, str): diff --git a/misoclib/mem/litesata/test/link_tb.py b/misoclib/mem/litesata/test/link_tb.py index def4e14d..142e14ed 100644 --- a/misoclib/mem/litesata/test/link_tb.py +++ b/misoclib/mem/litesata/test/link_tb.py @@ -1,8 +1,8 @@ -from litesata.common import * -from litesata.core.link import LiteSATALink +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link import LiteSATALink -from litesata.test.common import * -from litesata.test.hdd import * +from misoclib.mem.litesata.test.common import * +from misoclib.mem.litesata.test.hdd import * class LinkStreamer(PacketStreamer): def __init__(self): diff --git a/misoclib/mem/litesata/test/phy_datapath_tb.py b/misoclib/mem/litesata/test/phy_datapath_tb.py index a1c2d4c5..a78cc2fd 100644 --- a/misoclib/mem/litesata/test/phy_datapath_tb.py +++ b/misoclib/mem/litesata/test/phy_datapath_tb.py @@ -1,7 +1,7 @@ -from litesata.common import * -from litesata.phy.datapath import LiteSATAPHYDatapath +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.phy.datapath import LiteSATAPHYDatapath -from litesata.test.common import * +from misoclib.mem.litesata.test.common import * class DataPacket(list): def __init__(self, data=[]): diff --git a/misoclib/mem/litesata/test/scrambler_tb.py b/misoclib/mem/litesata/test/scrambler_tb.py index 11d626b1..20c4045c 100644 --- a/misoclib/mem/litesata/test/scrambler_tb.py +++ b/misoclib/mem/litesata/test/scrambler_tb.py @@ -1,9 +1,9 @@ import subprocess -from litesata.common import * -from litesata.core.link.scrambler import * +from misoclib.mem.litesata.common import * +from misoclib.mem.litesata.core.link.scrambler import * -from litesata.test.common import * +from misoclib.mem.litesata.test.common import * class TB(Module): def __init__(self, length): -- 2.30.2