From 0dfdbd991afcbcc38110d22d489969ae33fb1f68 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 19 Nov 2013 20:35:31 +0100 Subject: [PATCH] Fixed parsing of module arguments when one type is used for many args --- frontends/verilog/parser.y | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 17f14d541..1dcc0d6cc 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -248,9 +248,16 @@ optional_comma: module_arg: TOK_ID range { - if (port_stubs.count(*$1) != 0) - frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); - port_stubs[*$1] = ++port_counter; + if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { + AstNode *node = ast_stack.back()->children.back()->clone(); + node->str = *$1; + node->port_id = ++port_counter; + ast_stack.back()->children.push_back(node); + } else { + if (port_stubs.count(*$1) != 0) + frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); + port_stubs[*$1] = ++port_counter; + } if ($2 != NULL) delete $2; delete $1; -- 2.30.2