From 0e03cebd10fd68c4e9feaf30ab732d698f73e587 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Tue, 25 Apr 2017 14:03:19 +0200 Subject: [PATCH] [ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for CMP insns. gcc/ 2017-04-25 Claudiu Zissulescu * config/arc/arc.md (cmpsi_cc_insn_mixed): Use 'h' register constraint. (cmpsi_cc_c_insn): Likewise. (cbranchsi4_scratch): Compute proper instruction length using compact_hreg_operand. * config/arc/predicates.md (compact_hreg_operand): New predicate. From-SVN: r247194 --- gcc/ChangeLog | 9 +++++++++ gcc/config/arc/arc.md | 28 ++++++++++++++++------------ gcc/config/arc/predicates.md | 13 +++++++++++++ 3 files changed, 38 insertions(+), 12 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 83f0adc3d3f..7fb9ee86c28 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-04-25 Claudiu Zissulescu + + * config/arc/arc.md (cmpsi_cc_insn_mixed): Use 'h' register + constraint. + (cmpsi_cc_c_insn): Likewise. + (cbranchsi4_scratch): Compute proper instruction length using + compact_hreg_operand. + * config/arc/predicates.md (compact_hreg_operand): New predicate. + 2017-04-25 Richard Biener PR middle-end/80509 diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index f707bd0755e..802c3e90bdd 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -3458,15 +3458,16 @@ ;; modifed cc user if second, but not first operand is a compact register. (define_insn "cmpsi_cc_insn_mixed" [(set (reg:CC CC_REG) - (compare:CC (match_operand:SI 0 "register_operand" "Rcq#q, h, c, c,qRcq,c") - (match_operand:SI 1 "nonmemory_operand" "cO,Cm1,cI,cL, Cal,Cal")))] + (compare:CC (match_operand:SI 0 "register_operand" "Rcq#q,Rcqq, h, c, c,qRcq,c") + (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI,cL, Cal,Cal")))] "" "cmp%? %0,%B1%&" [(set_attr "type" "compare") - (set_attr "iscompact" "true,true,false,false,true_limm,false") - (set_attr "predicable" "no,no,no,yes,no,yes") + (set_attr "iscompact" "true,true,true,false,false,true_limm,false") + (set_attr "predicable" "no,no,no,no,yes,no,yes") (set_attr "cond" "set") - (set_attr "length" "*,*,4,4,*,8")]) + (set_attr "length" "*,*,*,4,4,*,8") + (set_attr "cpu_facility" "av1,av2,*,*,*,*,*")]) (define_insn "*cmpsi_cc_zn_insn" [(set (reg:CC_ZN CC_REG) @@ -3542,14 +3543,15 @@ (define_insn "*cmpsi_cc_c_insn" [(set (reg:CC_C CC_REG) - (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq, h, c,Rcqq, c") - (match_operand:SI 1 "nonmemory_operand" "cO,Cm1,cI, Cal,Cal")))] + (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq,Rcqq, h, c,Rcqq, c") + (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI, Cal,Cal")))] "" "cmp%? %0,%S1%&" [(set_attr "type" "compare") - (set_attr "iscompact" "true,true,false,true_limm,false") + (set_attr "iscompact" "true,true,true,false,true_limm,false") (set_attr "cond" "set") - (set_attr "length" "*,*,4,*,8")]) + (set_attr "length" "*,*,*,4,*,8") + (set_attr "cpu_facility" "av1,av2,*,*,*,*")]) ;; Next come the scc insns. @@ -4877,7 +4879,7 @@ return \"br%d0%* %1, %B2, %^%l3\"; /* FALLTHRU */ case 6: case 10: - case 12:return \"cmp%? %1, %B2\\n\\tb%d0%* %^%l3%&;br%d0 out of range\"; + case 12:return \"cmp%? %1, %B2\\n\\tb%d0%* %^%l3%& ;br%d0 out of range\"; default: fprintf (stderr, \"unexpected length %d\\n\", get_attr_length (insn)); fflush (stderr); gcc_unreachable (); } " @@ -4907,13 +4909,15 @@ (minus (const_int 244) (symbol_ref "get_attr_delay_slot_length (insn)")))) (const_int 4) - (match_operand:SI 1 "compact_register_operand" "") + (and (match_operand:SI 1 "compact_register_operand" "") + (match_operand:SI 2 "compact_hreg_operand" "")) (const_int 6)] (const_int 8))] (cond [(and (ge (minus (match_dup 3) (pc)) (const_int -256)) (le (minus (match_dup 3) (pc)) (const_int 244))) (const_int 8) - (match_operand:SI 1 "compact_register_operand" "") + (and (match_operand:SI 1 "compact_register_operand" "") + (match_operand:SI 2 "compact_hreg_operand" "")) (const_int 10)] (const_int 12)))) (set (attr "iscompact") diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index 9e60cb77328..f4c2a80f2be 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -189,6 +189,19 @@ } ) +(define_predicate "compact_hreg_operand" + (match_code "reg, subreg") + { + if ((GET_MODE (op) != mode) && (mode != VOIDmode)) + return 0; + + return (GET_CODE (op) == REG) + && (REGNO (op) >= FIRST_PSEUDO_REGISTER + || (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30) + || !TARGET_V2); + } +) + ;; Return true if OP is an acceptable memory operand for ARCompact ;; 16-bit store instructions (define_predicate "compact_store_memory_operand" -- 2.30.2