From 0e0ae69cc1273971048eb774189b00cc7317481f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 14 May 2022 16:19:12 +0100 Subject: [PATCH] --- openpower/sv/biginteger.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index e92ba87d3..c9ccf5570 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -38,7 +38,9 @@ fashion that is hidden from the user, behind a consistent, stable ISA API. **DRAFT** -`madded` is VA-Form: +`madded` is similar to v3.0 `madd`. +`madded`, like `madd`, is VA-Form despite having 2 outputs: the second +destination register is implicit. |0.....5|6..10|11..15|16..20|21..25|26..31| |-------|-----|------|------|------|------| @@ -49,7 +51,7 @@ The pseudocode for `madded RT, RA, RB, RC` is: prod[0:127] = (RA) * (RB) sum[0:127] = EXTZ(RC) + prod RT <- sum[64:127] - RS <- sum[0:63] # RS is either RC or RT+VL + RS <- sum[0:63] # RS is either RC or RT+MAXVL RC is zero-extended (not shifted), the 128-bit product added to it; the lower half of that result stored in RT and the upper half @@ -75,7 +77,7 @@ used with the additional bit set for determining RS. When `EXTRA2_MODE` is set to zero, the implicit RS register takes its Vector/Scalar setting from Rdest_EXTRA2, and takes the register number from RT, but all numbering -is offset by VL. *Note that element-width overrides influence this +is offset by MAXVL. *Note that element-width overrides influence this offset* (see SVP64 [[svp64/appendix]] for full details). When `EXTRA2_MODE` is set to one, the implicit RS register is identical -- 2.30.2