From 0e0cc1134d8314cd42ff6349099a1f2c156780d9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 29 Jul 2019 21:38:13 +0100 Subject: [PATCH] add explicit operator comparison (in case operation enum is changed) --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 1cf76b1d..8d5e1602 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -251,7 +251,7 @@ class DivPipeCoreSetupStage(Elaboratable): comb += lhs.eq(self.i.dividend << fw) with m.Elif(self.i.operation == int(DP.SqrtRem)): comb += lhs.eq(self.i.divisor_radicand << (fw * 2)) - with m.Else(): # DivPipeCoreOperation.RSqrtRem + with m.Elif(self.i.operation == int(DP.RSqrtRem)): comb += lhs.eq(1 << (fw * 3)) comb += self.o.compare_lhs.eq(lhs) @@ -324,7 +324,7 @@ class Trial(Elaboratable): comb += self.trial_compare_rhs.eq(sqrt_rhs) # RSqrtRem - with m.Else(): + with m.Elif(self.operation == int(DP.RSqrtRem)): rr_times_trial_bits = Signal((tblen+1)*3, reset_less=True) comb += rr_times_trial_bits.eq(rr * trial_bits_sig) rsqrt_rhs = self.compare_rhs -- 2.30.2