From 0e189558cf37aa1ba869a2f2359307b5425c93e5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 15 Mar 2020 19:24:13 +0000 Subject: [PATCH] Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility --- da/50cce442a7f788f130e63fd4e1742de36aed1b | 74 +++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 da/50cce442a7f788f130e63fd4e1742de36aed1b diff --git a/da/50cce442a7f788f130e63fd4e1742de36aed1b b/da/50cce442a7f788f130e63fd4e1742de36aed1b new file mode 100644 index 0000000..45dde36 --- /dev/null +++ b/da/50cce442a7f788f130e63fd4e1742de36aed1b @@ -0,0 +1,74 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Sun, 15 Mar 2020 19:24:47 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jDYsR-000072-GD; Sun, 15 Mar 2020 19:24:47 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jDYsP-00006w-H7 + for libre-riscv-dev@lists.libre-riscv.org; Sun, 15 Mar 2020 19:24:45 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lkcl.net; + s=201607131; + h=Content-Type:To:Subject:Message-ID:Date:From:In-Reply-To:References:MIME-Version; + bh=l5GxfSIWvyR/0Azy88q/XPL6NawgZRUyZh10oyWIl7Q=; + b=JY5hnLjW36yy3fjfyE8OElYjps4dYboSYpdi1as2fbGcYWeEMuxpr+J24m3X+4mVOEcMQB6ujhNcrHqk7ojJOIX3BFv2ban54rm00Dpqfbx2zV5kxLB/EFzVK9RTOOxzicnn91qYLFqbpR0HjN+8sf017q2HIQLULXgQ3Q+rN2k=; +Received: from mail-lf1-f52.google.com ([209.85.167.52]) + by lkcl.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.84_2) (envelope-from ) id 1jDYsP-00088N-77 + for libre-riscv-dev@lists.libre-riscv.org; Sun, 15 Mar 2020 19:24:45 +0000 +Received: by mail-lf1-f52.google.com with SMTP id f3so1893047lfc.1 + for ; + Sun, 15 Mar 2020 12:24:29 -0700 (PDT) +X-Gm-Message-State: ANhLgQ1fk2/M48a9xiyOmPybcd3AJbMb7Ej15gAYi8aP6lNuIKUcWMB9 + C6f9Fgyk5vvgvKvuSj7dCBndGowL5zcKcK1tgXQ= +X-Google-Smtp-Source: ADFU+vvCiVqhrPs6NBAEzu9+G8tZQPVEDunsVxrZNygb8qI4S+XJ24fYj0yoPQPAnrStZuLUCm8nOQxOvytF0iaqVuo= +X-Received: by 2002:ac2:5219:: with SMTP id a25mr1654673lfl.107.1584300264412; + Sun, 15 Mar 2020 12:24:24 -0700 (PDT) +MIME-Version: 1.0 +References: <6AC4EFD4-AA30-42C7-855A-CE68A62F107F@gatech.edu> + + <20200315051018.svaw4aor7ifwn725@topoi.pooq.com> + + + + <1BB9EA49-275B-4365-963E-9FC21D574BB7@gatech.edu> + <16F24775-E25B-4E31-A1D4-145EB65FB1D8@gatech.edu> + + <75CA4609-370F-455E-A88D-50E3766D45D7@gatech.edu> + <098A8F9F-04F1-4E14-9A94-F69CCC3D8D3E@gatech.edu> +In-Reply-To: <098A8F9F-04F1-4E14-9A94-F69CCC3D8D3E@gatech.edu> +From: Luke Kenneth Casson Leighton +Date: Sun, 15 Mar 2020 19:24:13 +0000 +X-Gmail-Original-Message-ID: +Message-ID: +To: Libre-RISCV General Development +Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture + feasibility +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +T24gU3VuLCBNYXIgMTUsIDIwMjAgYXQgNzoyMCBQTSBJbW1hbnVlbCwgWWVob3dzaHVhIFUKPHlp +bW1hbnVlbDNAZ2F0ZWNoLmVkdT4gd3JvdGU6Cj4KPiBPciwgaXMgdGhlIGludGVybmFsIGZvcm1h +dCBzb21lIHNvcnQgb2YgaW50ZXJtZWRpYXRlIHRoYXQgYm90aCBSSVNDViBhbmQgUE9XRVIgaW5z +dHJ1Y3Rpb25zIG1hcCBkb3duIHRvPwoKeWVlZXMuCgpfX19fX19fX19fX19fX19fX19fX19fX19f +X19fX19fX19fX19fX19fX19fX19fXwpsaWJyZS1yaXNjdi1kZXYgbWFpbGluZyBsaXN0CmxpYnJl +LXJpc2N2LWRldkBsaXN0cy5saWJyZS1yaXNjdi5vcmcKaHR0cDovL2xpc3RzLmxpYnJlLXJpc2N2 +Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpYnJlLXJpc2N2LWRldgo= -- 2.30.2