From 0e62dacdf84f674c6780314b79f02562a8d7ea96 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Fri, 29 May 2020 08:09:14 -0300 Subject: [PATCH] Allow immediate assertion of go in the same cycle as rel --- src/soc/experiment/compalu_multi.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 5514135e..7b1938e5 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -10,7 +10,7 @@ its result(s) have been successfully stored in the regfile(s) Documented at http://libre-soc.org/3d_gpu/architecture/compunit """ -from nmigen.compat.sim import run_simulation +from nmigen.compat.sim import run_simulation, Settle from nmigen.cli import verilog, rtlil from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Cat, Const from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT) @@ -413,8 +413,8 @@ class CompUnitParallelTest: self.MIN_BUSY_LOW = 5 # Number of cycles to stall until the assertion of go. - # One positive, non-zero value, for each port. - self.RD_GO_DELAY = [3, 1] + # One value, for each port. Can be zero, for no delay. + self.RD_GO_DELAY = [0, 3] # store common data for the input operation of the processes # input operation: @@ -535,6 +535,13 @@ class CompUnitParallelTest: rel = yield self.dut.rd.rel[rd_idx] assert rel + # Before asserting "go", make sure "rel" has risen. + # The use of Settle allows "go" to be set combinatorially, + # rising on the same cycle as "rel". + yield Settle() + rel = yield self.dut.rd.rel[rd_idx] + assert rel + # assert go for one cycle yield self.dut.rd.go[rd_idx].eq(1) yield -- 2.30.2