From 0e7354d4087c72bc4da9b8a4a1786fb0ef5782ba Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Tue, 28 Sep 2021 20:18:33 +0200 Subject: [PATCH] update testcase for dcbz --- src/soc/experiment/test/test_compldst_multi_mmu.py | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/soc/experiment/test/test_compldst_multi_mmu.py b/src/soc/experiment/test/test_compldst_multi_mmu.py index aa1f64bf..a2a2c02f 100644 --- a/src/soc/experiment/test/test_compldst_multi_mmu.py +++ b/src/soc/experiment/test/test_compldst_multi_mmu.py @@ -59,16 +59,12 @@ def load_part(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False, # else b <-(RA) # EA <- b + (RB) RB needs to be read # verify that EA is correct first -def dcbz(dut, ra, ra_needed, rb): +def dcbz(dut, ra, zero_a, rb): print("LD_part", ra, ra_needed, rb) yield dut.oper_i.insn_type.eq(MicrOp.OP_DCBZ) - #yield dut.oper_i.data_len.eq(2) # half-word - #yield dut.oper_i.byte_reverse.eq(byterev) yield dut.src1_i.eq(ra) yield dut.src2_i.eq(rb) - #???yield dut.oper_i.zero_a.eq(zero_a) - #yield dut.oper_i.imm_data.imm.eq(imm) - #yield dut.oper_i.imm_data.ok.eq(imm_ok) + yield dut.oper_i.zero_a.eq(zero_a) yield dut.issue_i.eq(1) yield yield dut.issue_i.eq(0) @@ -76,7 +72,7 @@ def dcbz(dut, ra, ra_needed, rb): def ldst_sim(dut): - yield from dcbz(dut, 4, True, 3) # EA=7 + yield from dcbz(dut, 4, 0, 3) # EA=7 #yield from load_part(dut, 4, 0, 2) yield -- 2.30.2