From 0e760f2476bad71296663e00b06b74bf50c1fd23 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Jul 2019 13:43:53 +0100 Subject: [PATCH] start to get FP to INT working --- src/ieee754/fcvt/pipeline.py | 17 +++++++++++------ src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py | 2 +- src/ieee754/fpcommon/test/fpmux.py | 4 ++++ 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py index 04855b1f..05ad9241 100644 --- a/src/ieee754/fcvt/pipeline.py +++ b/src/ieee754/fcvt/pipeline.py @@ -107,6 +107,10 @@ class FPCVTFloatToIntMod(Elaboratable): with m.If(a1.exp_n127): m.d.comb += self.o.z.eq(0) + # unsigned, -ve, return 0 + with m.Elif((~signed) & a1.s): + m.d.comb += self.o.z.eq(0) + # signed, exp too big with m.Elif(signed & (a1.e > Const(mz-1, espec))): with m.If(a1.s): # negative FP, so negative overrun @@ -123,17 +127,18 @@ class FPCVTFloatToIntMod(Elaboratable): # ok exp should be in range: shift and round it with m.Else(): - mantissa = Signal(mz, reset_less=True) - l = [0] * ms + [1] + [a1.m] - m.d.comb += mantissa.eq(Cat(*l)) + mlen = max(a1.m_width, mz) + 5 + mantissa = Signal(mlen, reset_less=True) + l = [0] * 2 + [a1.m[:-1]] + [1] + m.d.comb += mantissa[-a1.m_width-3:].eq(Cat(*l)) m.d.comb += self.o.z.eq(mantissa) # shift - msr = FPEXPHigh(mz+3, espec[0]) + msr = FPEXPHigh(mlen, espec[0]) m.submodules.norm_exp = msr - m.d.comb += [msr.m_in[3:].eq(mantissa), + m.d.comb += [msr.m_in.eq(mantissa), msr.e_in.eq(a1.e), - msr.ediff.eq(Mux(signed, mz-1, mz)) + msr.ediff.eq(Mux(signed, mz-1, mz)-a1.e) ] of = Overflow() diff --git a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py index 592e5af0..ac962beb 100644 --- a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py +++ b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py @@ -59,7 +59,7 @@ def test_int_pipe_i32_f32(): def test_int_pipe_f16_ui16(): # XXX softfloat-3 doesn't have ui16_to_xxx so use ui32 instead. # should be fine. - dut = FPCVTF2IntMuxInOut(16, 32, 4, op_wid=1) + dut = FPCVTF2IntMuxInOut(16, 16, 4, op_wid=1) runfp(dut, 16, "test_fcvt_f2int_pipe_f16_ui16", Float16, fcvt_f16_ui32, True, n_vals=100) diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py index cf638c96..ef4fbdd0 100644 --- a/src/ieee754/fpcommon/test/fpmux.py +++ b/src/ieee754/fpcommon/test/fpmux.py @@ -182,6 +182,10 @@ def create_random(num_rows, width, single_op=False, n_vals=10): #op1 = 0x3001 #op1 = 0x3f2ad8eb + # f2int + #op1 = 0x4dc0 + op1 = 0x3b81 + vals.append((op1,)) else: op1 = randint(0, (1<