From 0ea76916e63f8fc556f5e8f5a46c196d317cd5ad Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 7 Jul 2012 07:15:04 +0200 Subject: [PATCH] r600g: move CB_TARGET_MASK setup into new cb_misc_state to remove some overhead from draw_vbo. This is a derived state. BTW, I've got no idea how compute interacts with 3D here, but it should use cb_misc_state, so that 3D and compute don't conflict. Reviewed-by: Alex Deucher Reviewed-by: Tom Stellard --- src/gallium/drivers/r600/evergreen_compute.c | 3 +-- .../drivers/r600/evergreen_compute_internal.c | 2 +- src/gallium/drivers/r600/evergreen_hw_context.c | 2 -- src/gallium/drivers/r600/evergreen_state.c | 17 +++++++++++++++++ src/gallium/drivers/r600/r600_hw_context.c | 2 +- src/gallium/drivers/r600/r600_pipe.h | 9 ++++++++- src/gallium/drivers/r600/r600_state.c | 17 +++++++++++++++++ src/gallium/drivers/r600/r600_state_common.c | 12 ++++++------ 8 files changed, 51 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index 0d3c9f33651..a88cad1246e 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -284,10 +284,9 @@ void evergreen_direct_dispatch( struct evergreen_compute_resource* res = get_empty_res(rctx->cs_shader, COMPUTE_RESOURCE_DISPATCH, 0); - struct r600_pipe_state * cb_state = rctx->states[R600_PIPE_STATE_FRAMEBUFFER]; /* Set CB_TARGET_MASK */ - r600_pipe_state_add_reg(cb_state, R_028238_CB_TARGET_MASK, rctx->cb_target_mask); + evergreen_reg_set(res, R_028238_CB_TARGET_MASK, rctx->compute_cb_target_mask); evergreen_reg_set(res, R_008958_VGT_PRIMITIVE_TYPE, V_008958_DI_PT_POINTLIST); diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.c b/src/gallium/drivers/r600/evergreen_compute_internal.c index eb86a348703..c5aad932c94 100644 --- a/src/gallium/drivers/r600/evergreen_compute_internal.c +++ b/src/gallium/drivers/r600/evergreen_compute_internal.c @@ -289,7 +289,7 @@ void evergreen_set_rat( * XXX: I think this is a potential spot for bugs once we start doing * GL interop. cb_target_mask may be modified in the 3D sections * of this driver. */ - pipe->ctx->cb_target_mask |= (0xf << (id * 4)); + pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4)); /* Get the CB register writes for the RAT */ diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index 2ab29c9821c..dcbe0a47919 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -66,7 +66,6 @@ static const struct r600_reg evergreen_context_reg_list[] = { {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0}, {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0}, {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0}, - {R_028238_CB_TARGET_MASK, 0, 0}, {R_02823C_CB_SHADER_MASK, 0, 0}, {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, @@ -326,7 +325,6 @@ static const struct r600_reg cayman_context_reg_list[] = { {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0}, {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0}, {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0}, - {R_028238_CB_TARGET_MASK, 0, 0}, {R_02823C_CB_SHADER_MASK, 0, 0}, {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 60825bc7244..61efa287bab 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1728,6 +1728,21 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, if (state->zsbuf) { evergreen_polygon_offset_update(rctx); } + + if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) { + rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; + r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); + } +} + +static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = rctx->cs; + struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; + unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1; + + r600_write_context_reg(cs, R_028238_CB_TARGET_MASK, + a->blend_colormask & fb_colormask); } static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) @@ -1862,6 +1877,8 @@ static void evergreen_emit_ps_constant_buffer(struct r600_context *rctx, struct void evergreen_init_state_functions(struct r600_context *rctx) { + r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0); + r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0); r600_atom_dirty(rctx, &rctx->db_misc_state.atom); r600_init_atom(&rctx->vertex_buffer_state, evergreen_emit_vertex_buffers, 0, 0); diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index cbb89143f2a..d387678978f 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -336,7 +336,6 @@ static const struct r600_reg r600_context_reg_list[] = { {R_028128_CB_CLEAR_BLUE, 0, 0}, {R_02812C_CB_CLEAR_ALPHA, 0, 0}, {R_02823C_CB_SHADER_MASK, 0, 0}, - {R_028238_CB_TARGET_MASK, 0, 0}, {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0}, {R_028414_CB_BLEND_RED, 0, 0}, {R_028418_CB_BLEND_GREEN, 0, 0}, @@ -1283,6 +1282,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags) r600_flush_framebuffer(ctx, false); /* Re-emit states. */ + r600_atom_dirty(ctx, &ctx->cb_misc_state.atom); r600_atom_dirty(ctx, &ctx->db_misc_state.atom); r600_atom_dirty(ctx, &ctx->vertex_buffer_state); diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 1b3cef1de06..ef27742d872 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -82,6 +82,12 @@ struct r600_db_misc_state { bool flush_depthstencil_enabled; }; +struct r600_cb_misc_state { + struct r600_atom atom; + unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ + unsigned nr_cbufs; +}; + enum r600_pipe_state_id { R600_PIPE_STATE_BLEND = 0, R600_PIPE_STATE_BLEND_COLOR, @@ -280,8 +286,8 @@ struct r600_context { struct r600_pipe_state *states[R600_PIPE_NSTATES]; struct r600_vertex_element *vertex_elements; struct pipe_framebuffer_state framebuffer; - unsigned cb_target_mask; unsigned fb_cb_shader_mask; + unsigned compute_cb_target_mask; unsigned sx_alpha_test_control; unsigned cb_shader_mask; unsigned db_shader_control; @@ -328,6 +334,7 @@ struct r600_context { struct r600_command_buffer start_compute_cs_cmd; struct r600_surface_sync_cmd surface_sync_cmd; struct r600_atom r6xx_flush_and_inv_cmd; + struct r600_cb_misc_state cb_misc_state; struct r600_db_misc_state db_misc_state; struct r600_atom vertex_buffer_state; struct r600_constbuf_state vs_constbuf_state; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 0ba7fade043..a7eb7b62cb4 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1691,6 +1691,21 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, if (state->zsbuf) { r600_polygon_offset_update(rctx); } + + if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) { + rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; + r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); + } +} + +static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = rctx->cs; + struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; + unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1; + + r600_write_context_reg(cs, R_028238_CB_TARGET_MASK, + a->blend_colormask & fb_colormask); } static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) @@ -1818,6 +1833,8 @@ static void r600_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_ void r600_init_state_functions(struct r600_context *rctx) { + r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0); + r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0); r600_atom_dirty(rctx, &rctx->db_misc_state.atom); r600_init_atom(&rctx->vertex_buffer_state, r600_emit_vertex_buffers, 0, 0); diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 2cf0171166e..0e071d0f9da 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -157,12 +157,16 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state) return; rstate = &blend->rstate; rctx->states[rstate->id] = rstate; - rctx->cb_target_mask = blend->cb_target_mask; /* Replace every bit except MULTIWRITE_ENABLE. */ rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE; rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE; rctx->dual_src_blend = blend->dual_src_blend; r600_context_pipe_state_set(rctx, rstate); + + if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) { + rctx->cb_misc_state.blend_colormask = blend->cb_target_mask; + r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); + } } void r600_set_blend_color(struct pipe_context *ctx, @@ -848,7 +852,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) struct r600_context *rctx = (struct r600_context *)ctx; struct pipe_draw_info info = *dinfo; struct pipe_index_buffer ib = {}; - unsigned prim, mask, ls_mask = 0; + unsigned prim, ls_mask = 0; struct r600_block *dirty_block = NULL, *next_block = NULL; struct r600_atom *state = NULL, *next_state = NULL; struct radeon_winsys_cs *cs = rctx->cs; @@ -890,14 +894,11 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) } } - mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1; - if (rctx->vgt.id != R600_PIPE_STATE_VGT) { rctx->vgt.id = R600_PIPE_STATE_VGT; rctx->vgt.nregs = 0; r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim); r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask); r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0); r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias); r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index); @@ -919,7 +920,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) rctx->vgt.nregs = 0; r600_pipe_state_mod_reg(&rctx->vgt, prim); r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode)); - r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask); r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask); r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); -- 2.30.2