From 0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 25 Apr 2019 18:08:05 -0700
Subject: [PATCH] Add test

---
 tests/various/split_shiftx.v  | 118 ++++++++++++++++++++++++++++++++++
 tests/various/split_shiftx.ys |  21 ++++++
 2 files changed, 139 insertions(+)
 create mode 100644 tests/various/split_shiftx.v
 create mode 100644 tests/various/split_shiftx.ys

diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v
new file mode 100644
index 000000000..dfcea3880
--- /dev/null
+++ b/tests/various/split_shiftx.v
@@ -0,0 +1,118 @@
+module split_shiftx_test01(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h3, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Sign bit is 1
+module split_shiftx_test02(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h3, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h1, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Non constant $macc
+module split_shiftx_test03(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ s, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Wrong constant $macc
+module split_shiftx_test04(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h2, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys
new file mode 100644
index 000000000..810348aa3
--- /dev/null
+++ b/tests/various/split_shiftx.ys
@@ -0,0 +1,21 @@
+read_verilog -icells split_shiftx.v
+split_shiftx
+
+cd split_shiftx_test01
+select -assert-count 3 t:$shiftx
+select -assert-count 0 t: t:$shiftx %n %i
+
+cd split_shiftx_test02
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test03
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test04
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-- 
2.30.2