From 0ec66b99691ab8a09d2e16bd562b700a6624579e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 16 Feb 2017 03:53:27 +0000 Subject: [PATCH] radeon/ac: add emit umsb shared code. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Since we shared imsb, makes sense to share umsb. Reviewed-by: Edward O'Callaghan Reviewed-by: Marek Olšák Signed-off-by: Dave Airlie --- src/amd/common/ac_llvm_build.c | 25 +++++++++++++++++++++++++ src/amd/common/ac_llvm_build.h | 4 ++++ 2 files changed, 29 insertions(+) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index dda2c0b9421..ed31a5606e8 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/common/ac_llvm_build.c @@ -788,3 +788,28 @@ ac_emit_imsb(struct ac_llvm_context *ctx, return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, ""); } + +LLVMValueRef +ac_emit_umsb(struct ac_llvm_context *ctx, + LLVMValueRef arg, + LLVMTypeRef dst_type) +{ + LLVMValueRef args[2] = { + arg, + LLVMConstInt(ctx->i32, 1, 0), + }; + LLVMValueRef msb = ac_emit_llvm_intrinsic(ctx, "llvm.ctlz.i32", + dst_type, args, ARRAY_SIZE(args), + AC_FUNC_ATTR_READNONE); + + /* The HW returns the last bit index from MSB, but TGSI/NIR wants + * the index from LSB. Invert it by doing "31 - msb". */ + msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false), + msb, ""); + + /* check for zero */ + return LLVMBuildSelect(ctx->builder, + LLVMBuildICmp(ctx->builder, LLVMIntEQ, arg, + LLVMConstInt(ctx->i32, 0, 0), ""), + LLVMConstInt(ctx->i32, -1, true), msb, ""); +} diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h index 0ff04e4c703..3258e5ef54a 100644 --- a/src/amd/common/ac_llvm_build.h +++ b/src/amd/common/ac_llvm_build.h @@ -186,6 +186,10 @@ LLVMValueRef ac_emit_imsb(struct ac_llvm_context *ctx, LLVMValueRef arg, LLVMTypeRef dst_type); +LLVMValueRef ac_emit_umsb(struct ac_llvm_context *ctx, + LLVMValueRef arg, + LLVMTypeRef dst_type); + #ifdef __cplusplus } #endif -- 2.30.2