From 0ed9383db130bc94413c96bae15ef2ca1ebd1970 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 18 Oct 2018 23:11:08 +0100 Subject: [PATCH] use unsigned long shift on sv csr setting --- riscv/processor.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 4431dcd..3586dc0 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -378,8 +378,8 @@ void processor_t::set_csr(int which, reg_t val) int clroffset = 2; if (xlen == 64) { - state.sv_csrs[tbidx+2].u = get_field(val, 0xffff<<32); - state.sv_csrs[tbidx+3].u = get_field(val, 0xffff<<48); + state.sv_csrs[tbidx+2].u = get_field(val, 0xffffUL<<32); + state.sv_csrs[tbidx+3].u = get_field(val, 0xffffUL<<48); clroffset = 4; } // clear out all CSRs above the one(s) being set: this ensures that @@ -439,8 +439,8 @@ void processor_t::set_csr(int which, reg_t val) int clroffset = 2; if (xlen == 64) { - state.sv_pred_csrs[tbidx+2].u = get_field(val, 0xffff<<32); - state.sv_pred_csrs[tbidx+3].u = get_field(val, 0xffff<<48); + state.sv_pred_csrs[tbidx+2].u = get_field(val, 0xffffUL<<32); + state.sv_pred_csrs[tbidx+3].u = get_field(val, 0xffffUL<<48); clroffset = 4; } for (int i = tbidx+clroffset; i < 16; i++) -- 2.30.2