From 0edd880c3fe71d60b144b822b94a116ec9c408b5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Sep 2018 02:17:49 +0100 Subject: [PATCH] clarify sv cam table --- riscv/sv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv/sv.h b/riscv/sv.h index ba40926..58e5724 100644 --- a/riscv/sv.h +++ b/riscv/sv.h @@ -5,6 +5,8 @@ // this table is for the CSRs (4? for RV32E, 16 for other types) // it's a CAM that's used to generate 2 tables (below) +// just as in RV, writing to entries in this CAM *clears* +// all entries with a higher index typedef struct { unsigned int type : 1; // 0=INT, 1=FP unsigned int regkey : 5; // 5 bits -- 2.30.2