From 0ef955ae98ec0f0c91a914d5d0d34819b5ed194b Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 15 Apr 2020 14:42:46 +0000 Subject: [PATCH] back.rtlil: translate enum decoders to Yosys enum attributes. Fixes #254. --- nmigen/back/rtlil.py | 9 +++++++-- nmigen/hdl/ast.py | 6 ++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 90c5ed9..120a354 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -306,10 +306,15 @@ class _ValueCompilerState: else: wire_name = signal.name + attrs = dict(signal.attrs) + if signal._enum_class is not None: + attrs["enum_base_type"] = signal._enum_class.__name__ + for value in signal._enum_class: + attrs["enum_value_{:0{}b}".format(value.value, signal.width)] = value.name + wire_curr = self.rtlil.wire(width=signal.width, name=wire_name, port_id=port_id, port_kind=port_kind, - attrs=signal.attrs, - src=src(signal.src_loc)) + attrs=attrs, src=src(signal.src_loc)) if signal in self.driven and self.driven[signal]: wire_next = self.rtlil.wire(width=signal.width, name=wire_curr + "$next", src=src(signal.src_loc)) diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index 7e42c2a..45dab3d 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -425,7 +425,7 @@ class Value(metaclass=ABCMeta): def rotate_left(self, offset): """Rotate left by constant modulo 2**len(self). - + Parameters ---------- offset : int @@ -443,7 +443,7 @@ class Value(metaclass=ABCMeta): def rotate_right(self, offset): """Rotate right by constant modulo 2**len(self). - + Parameters ---------- offset : int @@ -922,8 +922,10 @@ class Signal(Value, DUID): except ValueError: return str(value) self.decoder = enum_decoder + self._enum_class = decoder else: self.decoder = decoder + self._enum_class = None # Not a @classmethod because nmigen.compat requires it. @staticmethod -- 2.30.2