From 0f1690fd9514f7a282141a7ad57a06b334b6c1a4 Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Wed, 29 Jul 2015 14:16:51 -0700 Subject: [PATCH] i965/fs: use the NIR bit size when creating registers v2 (Iago): - Squashed bits from 'support double precission constant operands for the implementation of 64-bit emit_load_const'. - Do not use BRW_REGISTER_TYPE_D for all 32-bit registers since that breaks asserts and functionality for some piglit tests. Just keep 32-bit types untouched and add 64-bit support. - Use DF instead of Q for 64-bit registers. Otherwise the code we generate will use Q sometimes and DF others and we hit unwanted DF/Q conversions, so always use DF. v3 (Sam): - Mark 'reg_type' occurrences as const (Topi). Signed-off-by: Topi Pohjolainen Signed-off-by: Tapani Palli Signed-off-by: Abdiel Janulgue Signed-off-by: Iago Toral Quiroga Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 36 ++++++++++++++++++------ 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 905f5c15ce6..f8150c8e99e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -370,7 +370,9 @@ fs_visitor::nir_emit_impl(nir_function_impl *impl) unsigned array_elems = reg->num_array_elems == 0 ? 1 : reg->num_array_elems; unsigned size = array_elems * reg->num_components; - nir_locals[reg->index] = bld.vgrf(BRW_REGISTER_TYPE_F, size); + const brw_reg_type reg_type = + reg->bit_size == 32 ? BRW_REGISTER_TYPE_F : BRW_REGISTER_TYPE_DF; + nir_locals[reg->index] = bld.vgrf(reg_type, size); } nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg, @@ -1209,10 +1211,24 @@ void fs_visitor::nir_emit_load_const(const fs_builder &bld, nir_load_const_instr *instr) { - fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, instr->def.num_components); + const brw_reg_type reg_type = + instr->def.bit_size == 32 ? BRW_REGISTER_TYPE_D : BRW_REGISTER_TYPE_DF; + fs_reg reg = bld.vgrf(reg_type, instr->def.num_components); - for (unsigned i = 0; i < instr->def.num_components; i++) - bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i])); + switch (instr->def.bit_size) { + case 32: + for (unsigned i = 0; i < instr->def.num_components; i++) + bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i])); + break; + + case 64: + for (unsigned i = 0; i < instr->def.num_components; i++) + bld.MOV(offset(reg, bld, i), brw_imm_df(instr->value.f64[i])); + break; + + default: + unreachable("Invalid bit size"); + } nir_ssa_values[instr->def.index] = reg; } @@ -1220,8 +1236,10 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld, void fs_visitor::nir_emit_undef(const fs_builder &bld, nir_ssa_undef_instr *instr) { - nir_ssa_values[instr->def.index] = bld.vgrf(BRW_REGISTER_TYPE_D, - instr->def.num_components); + const brw_reg_type reg_type = + instr->def.bit_size == 32 ? BRW_REGISTER_TYPE_D : BRW_REGISTER_TYPE_DF; + nir_ssa_values[instr->def.index] = + bld.vgrf(reg_type, instr->def.num_components); } fs_reg @@ -1248,8 +1266,10 @@ fs_reg fs_visitor::get_nir_dest(nir_dest dest) { if (dest.is_ssa) { - nir_ssa_values[dest.ssa.index] = bld.vgrf(BRW_REGISTER_TYPE_F, - dest.ssa.num_components); + const brw_reg_type reg_type = + dest.ssa.bit_size == 32 ? BRW_REGISTER_TYPE_F : BRW_REGISTER_TYPE_DF; + nir_ssa_values[dest.ssa.index] = + bld.vgrf(reg_type, dest.ssa.num_components); return nir_ssa_values[dest.ssa.index]; } else { /* We don't handle indirects on locals */ -- 2.30.2