From 0f37323cc3a2bbb35514d09127556446c64194d9 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sun, 20 Oct 2013 07:17:47 +0000 Subject: [PATCH] mips.h (ISA_HAS_WSBH): Define. gcc/ * config/mips/mips.h (ISA_HAS_WSBH): Define. * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New constants. (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns. gcc/testsuite/ * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c, gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c, gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests. From-SVN: r203870 --- gcc/ChangeLog | 7 ++++ gcc/config/mips/mips.h | 5 +++ gcc/config/mips/mips.md | 55 +++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 6 +++ gcc/testsuite/gcc.target/mips/bswap-1.c | 10 +++++ gcc/testsuite/gcc.target/mips/bswap-2.c | 9 ++++ gcc/testsuite/gcc.target/mips/bswap-3.c | 14 +++++++ gcc/testsuite/gcc.target/mips/bswap-4.c | 10 +++++ gcc/testsuite/gcc.target/mips/bswap-5.c | 20 +++++++++ gcc/testsuite/gcc.target/mips/bswap-6.c | 12 ++++++ 10 files changed, 148 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/bswap-1.c create mode 100644 gcc/testsuite/gcc.target/mips/bswap-2.c create mode 100644 gcc/testsuite/gcc.target/mips/bswap-3.c create mode 100644 gcc/testsuite/gcc.target/mips/bswap-4.c create mode 100644 gcc/testsuite/gcc.target/mips/bswap-5.c create mode 100644 gcc/testsuite/gcc.target/mips/bswap-6.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1915f095b52..8f42aedf88f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-10-20 Richard Sandiford + + * config/mips/mips.h (ISA_HAS_WSBH): Define. + * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New + constants. + (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns. + 2013-10-19 John David Anglin PR target/58603 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index af7eeee6682..c4a2a4a6862 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -972,6 +972,11 @@ struct mips_cpu_info { || TARGET_SMARTMIPS) \ && !TARGET_MIPS16) +/* ISA has the WSBH (word swap bytes within halfwords) instruction. + 64-bit targets also provide DSBH and DSHD. */ +#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \ + && !TARGET_MIPS16) + /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || TARGET_LOONGSON_2EF \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 0cda169224f..3554beb3033 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -74,6 +74,11 @@ UNSPEC_STORE_LEFT UNSPEC_STORE_RIGHT + ;; Integer operations that are too cumbersome to describe directly. + UNSPEC_WSBH + UNSPEC_DSBH + UNSPEC_DSHD + ;; Floating-point moves. UNSPEC_LOAD_LOW UNSPEC_LOAD_HIGH @@ -5358,6 +5363,56 @@ } [(set_attr "type" "shift") (set_attr "mode" "")]) + +(define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (bswap:HI (match_operand:HI 1 "register_operand" "d")))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn_and_split "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (bswap:SI (match_operand:SI 1 "register_operand" "d")))] + "ISA_HAS_WSBH && ISA_HAS_ROR" + "#" + "" + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) + (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] + "" + [(set_attr "insn_count" "2")]) + +(define_insn_and_split "bswapdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (bswap:DI (match_operand:DI 1 "register_operand" "d")))] + "TARGET_64BIT && ISA_HAS_WSBH" + "#" + "" + [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) + (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] + "" + [(set_attr "insn_count" "2")]) + +(define_insn "wsbh" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dsbh" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dshd" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dshd\t%0,%1" + [(set_attr "type" "shift")]) ;; ;; .................... diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2701f2628f6..ac6691c3c0c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2013-10-20 Richard Sandiford + + * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c, + gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c, + gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests. + 2013-10-19 John David Anglin * c-c++-common/opaque-vector.c: Skip long double test on hppa. diff --git a/gcc/testsuite/gcc.target/mips/bswap-1.c b/gcc/testsuite/gcc.target/mips/bswap-1.c new file mode 100644 index 00000000000..24016f26931 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/bswap-1.c @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return ((x << 8) & 0xff00) | ((x >> 8) & 0xff); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/bswap-2.c b/gcc/testsuite/gcc.target/mips/bswap-2.c new file mode 100644 index 00000000000..e0ca496b6d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/bswap-2.c @@ -0,0 +1,9 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return __builtin_bswap16 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/bswap-3.c b/gcc/testsuite/gcc.target/mips/bswap-3.c new file mode 100644 index 00000000000..5d2086fd324 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/bswap-3.c @@ -0,0 +1,14 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return (((x << 24) & 0xff000000) + | ((x << 8) & 0xff0000) + | ((x >> 8) & 0xff00) + | ((x >> 24) & 0xff)); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/bswap-4.c b/gcc/testsuite/gcc.target/mips/bswap-4.c new file mode 100644 index 00000000000..ac37a011440 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/bswap-4.c @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/bswap-5.c b/gcc/testsuite/gcc.target/mips/bswap-5.c new file mode 100644 index 00000000000..45520e4ab85 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/bswap-5.c @@ -0,0 +1,20 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return (((x << 56) & 0xff00000000000000ull) + | ((x << 40) & 0xff000000000000ull) + | ((x << 24) & 0xff0000000000ull) + | ((x << 8) & 0xff00000000ull) + | ((x >> 8) & 0xff000000) + | ((x >> 24) & 0xff0000) + | ((x >> 40) & 0xff00) + | ((x >> 56) & 0xff)); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/bswap-6.c b/gcc/testsuite/gcc.target/mips/bswap-6.c new file mode 100644 index 00000000000..1145357fef1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/bswap-6.c @@ -0,0 +1,12 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return __builtin_bswap64 (x); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */ -- 2.30.2