From 0f4c1906bb82f03f77683b71e597ed4802fe316a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 27 Feb 2020 10:29:53 -0800 Subject: [PATCH] Small fixes --- README.md | 12 ++++++------ kernel/timinginfo.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 08d4cb0d7..79801d23f 100644 --- a/README.md +++ b/README.md @@ -364,13 +364,13 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. -- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9` - that this module describes a LUT with propagation delays described using - `specify` statements. +- The module attribute ``abc9_lut`` is an integer attribute indicating to + `abc9` that this module describes a LUT with an area cost of this value, and + propagation delays described using `specify` statements. -- The module attribute ``abc9_box`` is a boolean specifying a blackbox or - whitebox definition, with propagation delays described using `specify` - statements, for use by `abc9`. +- The module attribute ``abc9_box`` is a boolean specifying a black/white-box + definition, with propagation delays described using `specify` statements, for + use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 5a6f4aa28..4b77c02e8 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -18,8 +18,8 @@ * */ -#ifndef TIMINGARCS_H -#define TIMINGARCS_H +#ifndef TIMINGINFO_H +#define TIMINGINFO_H #include "kernel/yosys.h" -- 2.30.2