From 0f690eeec7305853f53a11d18619d8626d46f094 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 31 Jul 2019 12:27:07 +0100 Subject: [PATCH] more cleanup --- src/ieee754/fpadd/addstages.py | 9 +++++---- src/ieee754/fpmul/mul0.py | 33 +++++--------------------------- src/ieee754/fpmul/mul1.py | 35 +++++++--------------------------- 3 files changed, 17 insertions(+), 60 deletions(-) diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py index 75d931d1..76df0e87 100644 --- a/src/ieee754/fpadd/addstages.py +++ b/src/ieee754/fpadd/addstages.py @@ -1,6 +1,8 @@ -# IEEE Floating Point Adder (Single Precision) -# Copyright (C) Jonathan P Dawson 2013 -# 2013-12-12 +"""IEEE754 Floating Point Adder Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton + +""" from nmigen import Module from nmigen.cli import main, verilog @@ -18,7 +20,6 @@ from ieee754.fpadd.add1 import FPAddStage1Mod class FPAddAlignSingleAdd(DynamicPipe): def __init__(self, pspec): - #FPState.__init__(self, "align") self.pspec = pspec super().__init__(pspec) diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py index 656e9bc0..916d7898 100644 --- a/src/ieee754/fpmul/mul0.py +++ b/src/ieee754/fpmul/mul0.py @@ -1,12 +1,13 @@ -# IEEE Floating Point Muler (Single Precision) -# Copyright (C) Jonathan P Dawson 2013 -# 2013-12-12 +"""IEEE754 Floating Point Multiplier Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton + +""" from nmigen import Module, Signal, Cat, Elaboratable from nmigen.cli import main, verilog from ieee754.fpcommon.fpbase import FPNumBaseRecord -from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.denorm import FPSCData from ieee754.fpcommon.getop import FPPipeContext @@ -52,9 +53,6 @@ class FPMulStage0Mod(Elaboratable): def elaborate(self, platform): m = Module() - #m.submodules.mul0_in_a = self.i.a - #m.submodules.mul0_in_b = self.i.b - #m.submodules.mul0_out_z = self.o.z # store intermediate tests (and zero-extended mantissas) am0 = Signal(len(self.i.a.m)+1, reset_less=True) @@ -74,24 +72,3 @@ class FPMulStage0Mod(Elaboratable): m.d.comb += self.o.out_do_z.eq(self.i.out_do_z) m.d.comb += self.o.ctx.eq(self.i.ctx) return m - - -class FPMulStage0(FPState): - """ First stage of mul. - """ - - def __init__(self, width, id_wid): - FPState.__init__(self, "multiply_0") - self.mod = FPMulStage0Mod(width) - self.o = self.mod.ospec() - - def setup(self, m, i): - """ links module to inputs and outputs - """ - self.mod.setup(m, i) - - # NOTE: these could be done as combinatorial (merge mul0+mul1) - m.d.sync += self.o.eq(self.mod.o) - - def action(self, m): - m.next = "multiply_1" diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py index 6d2f9ff4..6aa20561 100644 --- a/src/ieee754/fpmul/mul1.py +++ b/src/ieee754/fpmul/mul1.py @@ -1,14 +1,17 @@ -# IEEE Floating Point Multiplier +"""IEEE754 Floating Point Multiplier Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton + +""" from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog -from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.postcalc import FPAddStage1Data -from .mul0 import FPMulStage0Data +from ieee754.fpmul.mul0 import FPMulStage0Data -class FPMulStage1Mod(FPState, Elaboratable): +class FPMulStage1Mod(Elaboratable): """ Second stage of mul: preparation for normalisation. """ @@ -64,27 +67,3 @@ class FPMulStage1Mod(FPState, Elaboratable): m.d.comb += self.o.ctx.eq(self.i.ctx) return m - - -class FPMulStage1(FPState): - - def __init__(self, pspec): - FPState.__init__(self, "multiply_1") - width = pspec.width - self.mod = FPMulStage1Mod(pspec) - self.out_z = FPNumBaseRecord(width, False) - self.norm_stb = Signal() - - def setup(self, m, i): - """ links module to inputs and outputs - """ - self.mod.setup(m, i) - - m.d.sync += self.norm_stb.eq(0) # sets to zero when not in mul1 state - - m.d.sync += self.out_z.eq(self.mod.out_z) - m.d.sync += self.norm_stb.eq(1) - - def action(self, m): - m.next = "normalise_1" - -- 2.30.2