From 0f73cb1a1674020bff68c184b85bc349a356a2a7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 13:55:33 +0100 Subject: [PATCH] add sv categories --- simple_v_extension/opcodes.mdwn | 394 ++++++++++++++++---------------- 1 file changed, 197 insertions(+), 197 deletions(-) diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn index 851d63e89..f52722dbe 100644 --- a/simple_v_extension/opcodes.mdwn +++ b/simple_v_extension/opcodes.mdwn @@ -7,12 +7,12 @@ |auipc | rd oimm20 | u+o | rv32i rv64i rv128i | - | |jal | rd jimm20 | uj | rv32i rv64i rv128i | - | |jalr | rd rs1 oimm12 | i+o | rv32i rv64i rv128i | - | -|beq | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | -|bne | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | -|blt | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | -|bge | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | -|bltu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | -|bgeu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | +|beq | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR | +|bne | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR | +|blt | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR | +|bge | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR | +|bltu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR | +|bgeu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR | |lb | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vls | |lh | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vls | |lw | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vls | @@ -50,18 +50,18 @@ |lwu | rd rs1 oimm12 | i+l | rv64i rv128i | vls | |ld | rd rs1 oimm12 | i+l | rv64i rv128i | vls | |sd | rs1 rs2 simm12 | s | rv64i rv128i | vls | -|slli | rd rs1 shamt6 | i·sh6 | rv64i | | -|srli | rd rs1 shamt6 | i·sh6 | rv64i | | -|srai | rd rs1 shamt6 | i·sh6 | rv64i | | -|addiw | rd rs1 imm12 | i | rv64i rv128i | | -|slliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | | -|srliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | | -|sraiw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | | -|addw | rd rs1 rs2 | r | rv64i rv128i | | -|subw | rd rs1 rs2 | r | rv64i rv128i | | -|sllw | rd rs1 rs2 | r | rv64i rv128i | | -|srlw | rd rs1 rs2 | r | rv64i rv128i | | -|sraw | rd rs1 rs2 | r | rv64i rv128i | | +|slli | rd rs1 shamt6 | i·sh6 | rv64i | sv | +|srli | rd rs1 shamt6 | i·sh6 | rv64i | sv | +|srai | rd rs1 shamt6 | i·sh6 | rv64i | sv | +|addiw | rd rs1 imm12 | i | rv64i rv128i | sv | +|slliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv | +|srliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv | +|sraiw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv | +|addw | rd rs1 rs2 | r | rv64i rv128i | sv | +|subw | rd rs1 rs2 | r | rv64i rv128i | sv | +|sllw | rd rs1 rs2 | r | rv64i rv128i | sv | +|srlw | rd rs1 rs2 | r | rv64i rv128i | sv | +|sraw | rd rs1 rs2 | r | rv64i rv128i | sv | # RV128I "RV128I Base Integer Instruction Set (in addition to RV64I)" @@ -70,51 +70,51 @@ |ldu | rd rs1 oimm12 | i+l | rv128i | vls | |lq | rd rs1 oimm12 | i+l | rv128i | vls | |sq | rs1 rs2 simm12 | s | rv128i | vls | -|slli | rd rs1 shamt7 | i·sh7 | rv128i | | -|srli | rd rs1 shamt7 | i·sh7 | rv128i | | -|srai | rd rs1 shamt7 | i·sh7 | rv128i | | -|addid | rd rs1 imm12 | i | rv128i | | -|sllid | rd rs1 shamt6 | i·sh6 | rv128i | | -|srlid | rd rs1 shamt6 | i·sh6 | rv128i | | -|sraid | rd rs1 shamt6 | i·sh6 | rv128i | | -|addd | rd rs1 rs2 | r | rv128i | | -|subd | rd rs1 rs2 | r | rv128i | | -|slld | rd rs1 rs2 | r | rv128i | | -|srld | rd rs1 rs2 | r | rv128i | | -|srad | rd rs1 rs2 | r | rv128i | | +|slli | rd rs1 shamt7 | i·sh7 | rv128i | sv | +|srli | rd rs1 shamt7 | i·sh7 | rv128i | sv | +|srai | rd rs1 shamt7 | i·sh7 | rv128i | sv | +|addid | rd rs1 imm12 | i | rv128i | sv | +|sllid | rd rs1 shamt6 | i·sh6 | rv128i | sv | +|srlid | rd rs1 shamt6 | i·sh6 | rv128i | sv | +|sraid | rd rs1 shamt6 | i·sh6 | rv128i | sv | +|addd | rd rs1 rs2 | r | rv128i | sv | +|subd | rd rs1 rs2 | r | rv128i | sv | +|slld | rd rs1 rs2 | r | rv128i | sv | +|srld | rd rs1 rs2 | r | rv128i | sv | +|srad | rd rs1 rs2 | r | rv128i | sv | # RV32M "RV32M Standard Extension for Integer Multiply and Divide" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|mul | rd rs1 rs2 | r | rv32m rv64m rv128m | | -|mulh | rd rs1 rs2 | r | rv32m rv64m rv128m | | -|mulhsu | rd rs1 rs2 | r | rv32m rv64m rv128m | | -|mulhu | rd rs1 rs2 | r | rv32m rv64m rv128m | | -|div | rd rs1 rs2 | r | rv32m rv64m rv128m | | -|divu | rd rs1 rs2 | r | rv32m rv64m rv128m | | -|rem | rd rs1 rs2 | r | rv32m rv64m rv128m | | -|remu | rd rs1 rs2 | r | rv32m rv64m rv128m | | +|mul | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | +|mulh | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | +|mulhsu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | +|mulhu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | +|div | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | +|divu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | +|rem | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | +|remu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv | # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|mulw | rd rs1 rs2 | r | rv64m rv128m | | -|divw | rd rs1 rs2 | r | rv64m rv128m | | -|divuw | rd rs1 rs2 | r | rv64m rv128m | | -|remw | rd rs1 rs2 | r | rv64m rv128m | | -|remuw | rd rs1 rs2 | r | rv64m rv128m | | +|mulw | rd rs1 rs2 | r | rv64m rv128m | sv | +|divw | rd rs1 rs2 | r | rv64m rv128m | sv | +|divuw | rd rs1 rs2 | r | rv64m rv128m | sv | +|remw | rd rs1 rs2 | r | rv64m rv128m | sv | +|remuw | rd rs1 rs2 | r | rv64m rv128m | sv | # RV128M "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|muld | rd rs1 rs2 | r | rv128m | | -|divd | rd rs1 rs2 | r | rv128m | | -|divud | rd rs1 rs2 | r | rv128m | | -|remd | rd rs1 rs2 | r | rv128m | | -|remud | rd rs1 rs2 | r | rv128m | | +|muld | rd rs1 rs2 | r | rv128m | sv | +|divd | rd rs1 rs2 | r | rv128m | sv | +|divud | rd rs1 rs2 | r | rv128m | sv | +|remd | rd rs1 rs2 | r | rv128m | sv | +|remud | rd rs1 rs2 | r | rv128m | sv | # RV32A "RV32A Standard Extension for Atomic Instructions" @@ -122,47 +122,47 @@ | -------- | -------- | ------- | ------- | | |lr.w | rd rs1 | r·l | rv32a rv64a rv128a | - | |sc.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | - | -|amoswap.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amoadd.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amoxor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amoor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amoand.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amomin.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amomax.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amominu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | | -|amomaxu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | | +|amoswap.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amoadd.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amoxor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amoor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amoand.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amomin.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amomax.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amominu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | +|amomaxu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|lr.d | rd rs1 | r·l | rv64a rv128a | | -|sc.d | rd rs1 rs2 | r·a | rv64a rv128a | | -|amoswap.d| rd rs1 rs2 | r·a | rv64a rv128a | | -|amoadd.d | rd rs1 rs2 | r·a | rv64a rv128a | | -|amoxor.d | rd rs1 rs2 | r·a | rv64a rv128a | | -|amoor.d | rd rs1 rs2 | r·a | rv64a rv128a | | -|amoand.d | rd rs1 rs2 | r·a | rv64a rv128a | | -|amomin.d | rd rs1 rs2 | r·a | rv64a rv128a | | -|amomax.d | rd rs1 rs2 | r·a | rv64a rv128a | | -|amominu.d| rd rs1 rs2 | r·a | rv64a rv128a | | -|amomaxu.d| rd rs1 rs2 | r·a | rv64a rv128a | | +|lr.d | rd rs1 | r·l | rv64a rv128a | - | +|sc.d | rd rs1 rs2 | r·a | rv64a rv128a | - | +|amoswap.d| rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amoadd.d | rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amoxor.d | rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amoor.d | rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amoand.d | rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amomin.d | rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amomax.d | rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amominu.d| rd rs1 rs2 | r·a | rv64a rv128a | sv | +|amomaxu.d| rd rs1 rs2 | r·a | rv64a rv128a | sv | # RV128A "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|lr.q | rd rs1 | r·l | rv128a | | -|sc.q | rd rs1 rs2 | r·a | rv128a | | -|amoswap.q| rd rs1 rs2 | r·a | rv128a | | -|amoadd.q | rd rs1 rs2 | r·a | rv128a | | -|amoxor.q | rd rs1 rs2 | r·a | rv128a | | -|amoor.q | rd rs1 rs2 | r·a | rv128a | | -|amoand.q | rd rs1 rs2 | r·a | rv128a | | -|amomin.q | rd rs1 rs2 | r·a | rv128a | | -|amomax.q | rd rs1 rs2 | r·a | rv128a | | -|amominu.q| rd rs1 rs2 | r·a | rv128a | | -|amomaxu.q| rd rs1 rs2 | r·a | rv128a | | +|lr.q | rd rs1 | r·l | rv128a | - | +|sc.q | rd rs1 rs2 | r·a | rv128a | - | +|amoswap.q| rd rs1 rs2 | r·a | rv128a | sv | +|amoadd.q | rd rs1 rs2 | r·a | rv128a | sv | +|amoxor.q | rd rs1 rs2 | r·a | rv128a | sv | +|amoor.q | rd rs1 rs2 | r·a | rv128a | sv | +|amoand.q | rd rs1 rs2 | r·a | rv128a | sv | +|amomin.q | rd rs1 rs2 | r·a | rv128a | sv | +|amomax.q | rd rs1 rs2 | r·a | rv128a | sv | +|amominu.q| rd rs1 rs2 | r·a | rv128a | sv | +|amomaxu.q| rd rs1 rs2 | r·a | rv128a | sv | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" @@ -178,143 +178,143 @@ |sfence.vm | rs1 | r+sf | rv32s rv64s rv128s | - | |sfence.vma| rs1 rs2 | r+sfa | rv32s rv64s rv128s | - | |wfi | | none | rv32s rv64s rv128s | - | -|csrrw | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | | -|csrrs | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | | -|csrrc | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | | -|csrrwi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | | -|csrrsi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | | -|csrrci | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | | +|csrrw | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? | +|csrrs | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? | +|csrrc | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? | +|csrrwi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? | +|csrrsi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? | +|csrrci | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|flw | frd rs1 oimm12 | i+lf | rv32f rv64f rv128f | | -|fsw | rs1 frs2 simm12 | s+f | rv32f rv64f rv128f | | -|fmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | -|fmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | -|fnmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | -|fnmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | -|fadd.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | -|fsub.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | -|fmul.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | -|fdiv.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | -|fsgnj.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | -|fsgnjn.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | -|fsgnjx.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | -|fmin.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | -|fmax.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | -|fsqrt.s | frd frs1 rm | r·m+ff | rv32f rv64f rv128f | | -|fle.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | | -|flt.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | | -|feq.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | | -|fcvt.w.s | rd frs1 rm | r·m+rf | rv32f rv64f rv128f | | -|fcvt.wu.s| rd frs1 rm | r·m+rf | rv32f rv64f rv128f | | -|fcvt.s.w | frd rs1 rm | r·m+fr | rv32f rv64f rv128f | | -|fcvt.s.wu| frd rs1 rm | r·m+fr | rv32f rv64f rv128f | | -|fmv.x.s | rd frs1 | r+rf | rv32f rv64f rv128f | | -|fclass.s | rd frs1 | r+rf | rv32f rv64f rv128f | | -|fmv.s.x | frd rs1 | r+fr | rv32f rv64f rv128f | | +|flw | frd rs1 oimm12 | i+lf | rv32f rv64f rv128f | vld | +|fsw | rs1 frs2 simm12 | s+f | rv32f rv64f rv128f | vld | +|fmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv | +|fmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv | +|fnmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv | +|fnmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv | +|fadd.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv | +|fsub.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv | +|fmul.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv | +|fdiv.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv | +|fsgnj.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v | +|fsgnjn.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v | +|fsgnjx.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | sv | +|fmin.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | sv | +|fmax.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | sv | +|fsqrt.s | frd frs1 rm | r·m+ff | rv32f rv64f rv128f | sv | +|fle.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv | +|flt.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv | +|feq.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv | +|fcvt.w.s | rd frs1 rm | r·m+rf | rv32f rv64f rv128f | 2v | +|fcvt.wu.s| rd frs1 rm | r·m+rf | rv32f rv64f rv128f | 2v | +|fcvt.s.w | frd rs1 rm | r·m+fr | rv32f rv64f rv128f | 2v | +|fcvt.s.wu| frd rs1 rm | r·m+fr | rv32f rv64f rv128f | 2v | +|fmv.x.s | rd frs1 | r+rf | rv32f rv64f rv128f | 2v | +|fclass.s | rd frs1 | r+rf | rv32f rv64f rv128f | sv | +|fmv.s.x | frd rs1 | r+fr | rv32f rv64f rv128f | 2v | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|fcvt.l.s | rd frs1 rm | r·m+rf | rv64f rv128f | | -|fcvt.lu.s| rd frs1 rm | r·m+rf | rv64f rv128f | | -|fcvt.s.l | frd rs1 rm | r·m+fr | rv64f rv128f | | -|fcvt.s.lu| frd rs1 rm | r·m+fr | rv64f rv128f | | +|fcvt.l.s | rd frs1 rm | r·m+rf | rv64f rv128f | 2v | +|fcvt.lu.s| rd frs1 rm | r·m+rf | rv64f rv128f | 2v | +|fcvt.s.l | frd rs1 rm | r·m+fr | rv64f rv128f | 2v | +|fcvt.s.lu| frd rs1 rm | r·m+fr | rv64f rv128f | 2v | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|fld | frd rs1 oimm12 | i+lf | rv32d rv64d rv128d | | -|fsd | rs1 frs2 simm12 | s+f | rv32d rv64d rv128d | | -|fmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | -|fmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | -|fnmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | -|fnmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | -|fadd.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | -|fsub.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | -|fmul.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | -|fdiv.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | -|fsgnj.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | -|fsgnjn.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | -|fsgnjx.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | -|fmin.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | -|fmax.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | -|fcvt.s.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | | -|fcvt.d.s | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | | -|fsqrt.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | | -|fle.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | | -|flt.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | | -|feq.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | | -|fcvt.w.d | rd frs1 rm | r·m+rf | rv32d rv64d rv128d | | -|fcvt.wu.d| rd frs1 rm | r·m+rf | rv32d rv64d rv128d | | -|fcvt.d.w | frd rs1 rm | r·m+fr | rv32d rv64d rv128d | | -|fcvt.d.wu| frd rs1 rm | r·m+fr | rv32d rv64d rv128d | | -|fclass.d | rd frs1 | r+rf | rv32d rv64d rv128d | | +|fld | frd rs1 oimm12 | i+lf | rv32d rv64d rv128d | vld | +|fsd | rs1 frs2 simm12 | s+f | rv32d rv64d rv128d | vld | +|fmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv | +|fmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv | +|fnmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv | +|fnmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv | +|fadd.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv | +|fsub.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv | +|fmul.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv | +|fdiv.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv | +|fsgnj.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v | +|fsgnjn.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v | +|fsgnjx.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v | +|fmin.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | sv | +|fmax.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | sv | +|fcvt.s.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | 2v | +|fcvt.d.s | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | 2v | +|fsqrt.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | sv | +|fle.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv | +|flt.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv | +|feq.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv | +|fcvt.w.d | rd frs1 rm | r·m+rf | rv32d rv64d rv128d | 2v | +|fcvt.wu.d| rd frs1 rm | r·m+rf | rv32d rv64d rv128d | 2v | +|fcvt.d.w | frd rs1 rm | r·m+fr | rv32d rv64d rv128d | 2v | +|fcvt.d.wu| frd rs1 rm | r·m+fr | rv32d rv64d rv128d | 2v | +|fclass.d | rd frs1 | r+rf | rv32d rv64d rv128d | sv | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|fcvt.l.d | rd frs1 rm | r·m+rf | rv64d rv128d | | -|fcvt.lu.d| rd frs1 rm | r·m+rf | rv64d rv128d | | -|fmv.x.d | rd frs1 | r+rf | rv64d rv128d | | -|fcvt.d.l | frd rs1 rm | r·m+fr | rv64d rv128d | | -|fcvt.d.lu| frd rs1 rm | r·m+fr | rv64d rv128d | | -|fmv.d.x | frd rs1 | r+fr | rv64d rv128d | | +|fcvt.l.d | rd frs1 rm | r·m+rf | rv64d rv128d | 2v | +|fcvt.lu.d| rd frs1 rm | r·m+rf | rv64d rv128d | 2v | +|fmv.x.d | rd frs1 | r+rf | rv64d rv128d | 2v | +|fcvt.d.l | frd rs1 rm | r·m+fr | rv64d rv128d | 2v | +|fcvt.d.lu| frd rs1 rm | r·m+fr | rv64d rv128d | 2v | +|fmv.d.x | frd rs1 | r+fr | rv64d rv128d | 2v | # RV32Q "RV32Q Standard Extension for Quad-Precision Floating-Point" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|flq | frd rs1 oimm12 | i+lf | rv32q rv64q rv128q | | -|fsq | rs1 frs2 simm12 | s+f | rv32q rv64q rv128q | | -|fmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | -|fmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | -|fnmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | -|fnmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | -|fadd.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | -|fsub.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | -|fmul.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | -|fdiv.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | -|fsgnj.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | -|fsgnjn.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | -|fsgnjx.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | -|fmin.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | -|fmax.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | -|fcvt.s.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | -|fcvt.q.s | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | -|fcvt.d.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | -|fcvt.q.d | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | -|fsqrt.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | -|fle.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | | -|flt.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | | -|feq.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | | -|fcvt.w.q | rd frs1 rm | r·m+rf | rv32q rv64q rv128q | | -|fcvt.wu.q| rd frs1 rm | r·m+rf | rv32q rv64q rv128q | | -|fcvt.q.w | frd rs1 rm | r·m+fr | rv32q rv64q rv128q | | -|fcvt.q.wu| frd rs1 rm | r·m+fr | rv32q rv64q rv128q | | -|fclass.q | rd frs1 | r+rf | rv32q rv64q rv128q | | +|flq | frd rs1 oimm12 | i+lf | rv32q rv64q rv128q | vls | +|fsq | rs1 frs2 simm12 | s+f | rv32q rv64q rv128q | vls | +|fmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv | +|fmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv | +|fnmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv | +|fnmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv | +|fadd.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv | +|fsub.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv | +|fmul.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv | +|fdiv.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv | +|fsgnj.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v | +|fsgnjn.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v | +|fsgnjx.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v | +|fmin.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | sv | +|fmax.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | sv | +|fcvt.s.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v | +|fcvt.q.s | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v | +|fcvt.d.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v | +|fcvt.q.d | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v | +|fsqrt.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | sv | +|fle.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv | +|flt.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv | +|feq.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv | +|fcvt.w.q | rd frs1 rm | r·m+rf | rv32q rv64q rv128q | 2v | +|fcvt.wu.q| rd frs1 rm | r·m+rf | rv32q rv64q rv128q | 2v | +|fcvt.q.w | frd rs1 rm | r·m+fr | rv32q rv64q rv128q | 2v | +|fcvt.q.wu| frd rs1 rm | r·m+fr | rv32q rv64q rv128q | 2v | +|fclass.q | rd frs1 | r+rf | rv32q rv64q rv128q | sv | # RV64Q "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|fcvt.l.q | rd frs1 rm | r·m+rf | rv64q rv128q | | -|fcvt.lu.q| rd frs1 rm | r·m+rf | rv64q rv128q | | -|fcvt.q.l | frd rs1 rm | r·m+fr | rv64q rv128q | | -|fcvt.q.lu| frd rs1 rm | r·m+fr | rv64q rv128q | | +|fcvt.l.q | rd frs1 rm | r·m+rf | rv64q rv128q | 2v | +|fcvt.lu.q| rd frs1 rm | r·m+rf | rv64q rv128q | 2v | +|fcvt.q.l | frd rs1 rm | r·m+fr | rv64q rv128q | 2v | +|fcvt.q.lu| frd rs1 rm | r·m+fr | rv64q rv128q | 2v | # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | -|fmv.x.q | rd frs1 | r+rf | rv64q rv128q | | -|fmv.q.x | frd rs1 | r+fr | rv64q rv128q | | +|fmv.x.q | rd frs1 | r+rf | rv64q rv128q | 2v | +|fmv.q.x | frd rs1 | r+fr | rv64q rv128q | 2v | # RV32C "RV32C Standard Extension for Compressed Instructions" @@ -327,25 +327,25 @@ |c.fsd | crs1q cfrs2q cimmd | cs·sd+f | rv32c rv64c | vls | |c.sw | crs1q crs2q cimmw | cs·sw | rv32c rv64c | vls | |c.fsw | crs1q cfrs2q cimmw | cs·sw+f | rv32c | vls | -|c.nop | | ci·none | rv32c rv64c | | -|c.addi | crs1rd cnzimmi | ci | rv32c rv64c | | +|c.nop | | ci·none | rv32c rv64c | - | +|c.addi | crs1rd cnzimmi | ci | rv32c rv64c | sv | |c.jal | cimmj | cj·jal | rv32c | - | |c.li | crs1rd cimmi | ci·li | rv32c rv64c | sv | |c.addi16sp|crs1rd cimm16sp | ci·16sp | rv32c rv64c | TODO: special-case in spike-sv (disable SV mode) | |c.lui | crd cimmui | ci·lui | rv32c rv64c | sv | -|c.srli | crs1rdq cimmsh5 | cb·sh5 | rv32c | | -|c.srai | crs1rdq cimmsh5 | cb·sh5 | rv32c | | -|c.andi | crs1rdq cnzimmi | cb·imm | rv32c rv64c | | -|c.sub | crs1rdq crs2q | cs | rv32c rv64c | | -|c.xor | crs1rdq crs2q | cs | rv32c rv64c | | -|c.or | crs1rdq crs2q | cs | rv32c rv64c | | -|c.and | crs1rdq crs2q | cs | rv32c rv64c | | -|c.subw | crs1rdq crs2q | cs | rv32c rv64c | | -|c.addw | crs1rdq crs2q | cs | rv32c rv64c | | +|c.srli | crs1rdq cimmsh5 | cb·sh5 | rv32c | sv | +|c.srai | crs1rdq cimmsh5 | cb·sh5 | rv32c | sv | +|c.andi | crs1rdq cnzimmi | cb·imm | rv32c rv64c | sv | +|c.sub | crs1rdq crs2q | cs | rv32c rv64c | sv | +|c.xor | crs1rdq crs2q | cs | rv32c rv64c | sv | +|c.or | crs1rdq crs2q | cs | rv32c rv64c | sv | +|c.and | crs1rdq crs2q | cs | rv32c rv64c | sv | +|c.subw | crs1rdq crs2q | cs | rv32c rv64c | sv | +|c.addw | crs1rdq crs2q | cs | rv32c rv64c | sv | |c.j | cimmj | cj | rv32c rv64c | - | -|c.beqz | crs1q cimmb | cb | rv32c rv64c | | -|c.bnez | crs1q cimmb | cb | rv32c rv64c | | -|c.slli | crs1rd cimmsh5 | ci·sh5 | rv32c | | +|c.beqz | crs1q cimmb | cb | rv32c rv64c | VBR | +|c.bnez | crs1q cimmb | cb | rv32c rv64c | VBR | +|c.slli | crs1rd cimmsh5 | ci·sh5 | rv32c | sv | |c.fldsp | cfrd cimmldsp | ci·ldsp+f | rv32c rv64c | VU | |c.lwsp | crd cimmlwsp | ci·lwsp | rv32c rv64c | VU | |c.flwsp | cfrd cimmlwsp | ci·lwsp+f | rv32c | VU | @@ -353,10 +353,10 @@ |c.mv | crd crs2 | cr·mv | rv32c rv64c | 2v | |c.ebreak | | ci·none | rv32c rv64c | - | |c.jalr | crd0 crs1 | cr·jalr | rv32c rv64c | - | -|c.add | crs1rd crs2 | cr | rv32c rv64c | | +|c.add | crs1rd crs2 | cr | rv32c rv64c | sv | |c.fsdsp | cfrs2 cimmsdsp | css·sdsp+f | rv32c rv64c | VU | |c.swsp | crs2 cimmswsp | css·swsp | rv32c rv64c | VU | -|c.fswsp | cfrs2 cimmswsp | css·swsp+f | rv32c | VU | +|c.fswsp | cfrs2 cimmswsp | css·swsp+f | rv32c | VU | # RV64C "RV64C Standard Extension for Compressed Instructions (in addition to RV32C)" -- 2.30.2