From 0f821ab34555f4654b022a89ebd0cf755d5327dc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 16 Jun 2019 14:38:51 +0100 Subject: [PATCH] fix several test imports, add Elaboratable --- src/TLB/ariane/ptw.py | 4 ++-- src/TLB/ariane/test/test_plru.py | 2 +- src/TLB/ariane/test/test_ptw.py | 10 ++++++---- src/TLB/ariane/test/test_tlb.py | 4 ++-- src/TLB/ariane/tlb.py | 6 +++--- src/TLB/ariane/tlb_content.py | 7 ++++--- 6 files changed, 18 insertions(+), 15 deletions(-) diff --git a/src/TLB/ariane/ptw.py b/src/TLB/ariane/ptw.py index 05ec2d7d..ace44d14 100644 --- a/src/TLB/ariane/ptw.py +++ b/src/TLB/ariane/ptw.py @@ -25,7 +25,7 @@ see linux kernel source: """ -from nmigen import Const, Signal, Cat, Module +from nmigen import Const, Signal, Cat, Module, Elaboratable from nmigen.hdl.ast import ArrayProxy from nmigen.cli import verilog, rtlil from math import log2 @@ -153,7 +153,7 @@ LVL2 = Const(1, 2) LVL3 = Const(2, 2) -class PTW: +class PTW(Elaboratable): def __init__(self, asid_width=8): self.asid_width = asid_width diff --git a/src/TLB/ariane/test/test_plru.py b/src/TLB/ariane/test/test_plru.py index b249f549..68dcfa58 100644 --- a/src/TLB/ariane/test/test_plru.py +++ b/src/TLB/ariane/test/test_plru.py @@ -2,7 +2,7 @@ import sys sys.path.append("../src") sys.path.append("../../../TestUtil") -from plru import PLRU +from TLB.ariane.plru import PLRU from nmigen.compat.sim import run_simulation diff --git a/src/TLB/ariane/test/test_ptw.py b/src/TLB/ariane/test/test_ptw.py index 3164501d..7a8a893d 100644 --- a/src/TLB/ariane/test/test_ptw.py +++ b/src/TLB/ariane/test/test_ptw.py @@ -7,7 +7,7 @@ from nmigen.compat.sim import run_simulation from TLB.ariane.ptw import PTW, PTE -def testbench(dut): +def tbench(dut): addr = 0x8000000 @@ -120,8 +120,10 @@ def testbench(dut): yield - -if __name__ == "__main__": +def test_ptw(): dut = PTW() - run_simulation(dut, testbench(dut), vcd_name="test_ptw.vcd") + run_simulation(dut, tbench(dut), vcd_name="test_ptw.vcd") print("PTW Unit Test Success") + +if __name__ == "__main__": + test_ptw() diff --git a/src/TLB/ariane/test/test_tlb.py b/src/TLB/ariane/test/test_tlb.py index ef52ba74..e10325f8 100644 --- a/src/TLB/ariane/test/test_tlb.py +++ b/src/TLB/ariane/test/test_tlb.py @@ -11,7 +11,7 @@ def set_vaddr(addr): yield dut.update_i.vpn.eq(addr>>12) -def testbench(dut): +def tbench(dut): yield dut.lu_access_i.eq(1) yield dut.lu_asid_i.eq(1) yield dut.update_i.valid.eq(1) @@ -66,4 +66,4 @@ def testbench(dut): if __name__ == "__main__": dut = TLB() - run_simulation(dut, testbench(dut), vcd_name="test_tlb.vcd") + run_simulation(dut, tbench(dut), vcd_name="test_tlb.vcd") diff --git a/src/TLB/ariane/tlb.py b/src/TLB/ariane/tlb.py index f768571e..31505118 100644 --- a/src/TLB/ariane/tlb.py +++ b/src/TLB/ariane/tlb.py @@ -29,9 +29,9 @@ from nmigen import Signal, Module, Cat, Const, Array from nmigen.cli import verilog, rtlil from nmigen.lib.coding import Encoder -from ptw import TLBUpdate, PTE, ASID_WIDTH -from plru import PLRU -from tlb_content import TLBContent +from TLB.ariane.ptw import TLBUpdate, PTE, ASID_WIDTH +from TLB.ariane.plru import PLRU +from TLB.ariane.tlb_content import TLBContent TLB_ENTRIES = 8 diff --git a/src/TLB/ariane/tlb_content.py b/src/TLB/ariane/tlb_content.py index 024c5697..5c005b84 100644 --- a/src/TLB/ariane/tlb_content.py +++ b/src/TLB/ariane/tlb_content.py @@ -1,6 +1,7 @@ -from nmigen import Signal, Module, Cat, Const +from nmigen import Signal, Module, Cat, Const, Elaboratable + +from TLB.ariane.ptw import TLBUpdate, PTE -from ptw import TLBUpdate, PTE class TLBEntry: def __init__(self, asid_width): @@ -23,7 +24,7 @@ class TLBEntry: return [self.asid, self.vpn0, self.vpn1, self.vpn2, self.is_2M, self.is_1G, self.valid] -class TLBContent: +class TLBContent(Elaboratable): def __init__(self, pte_width, asid_width): self.asid_width = asid_width self.pte_width = pte_width -- 2.30.2