From 0f82a78f792073749940f0c9583daf6e01183324 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Mar 2022 16:56:26 +0100 Subject: [PATCH] update code-comments --- lambdasoc/periph/hyperram.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py index 299a165..c9b5d94 100644 --- a/lambdasoc/periph/hyperram.py +++ b/lambdasoc/periph/hyperram.py @@ -24,9 +24,9 @@ use platform.add_extension to first define the pins: io = self.platform.request("hyperram") this trick will work with the 1-IC HyperRAM PMOD by Piotr Esden, sold -by 1bitsquared. however for the *four* IC HyperRAM PMOD, *four* -separate and distinct instances are needed, each with a different -cs_n pin. on the TODO list for this module: interleave multiple HyperRAM +by 1bitsquared. however for the *four* IC HyperRAM PMOD, *four* cs_n pins +are needed (and is not currently supported). +on the TODO list for this module: interleave multiple HyperRAM cs_n's to give striped (like RAID) memory accesses behind one single Wishbone interface. """ @@ -142,6 +142,7 @@ class HyperRAM(Peripheral, Elaboratable): - no setup/chip configuration (use default latency). This core favors portability and ease of use over performance. + Tested: Winbond W956D8MBYA latency=7 """ def __init__(self, *, io, phy_kls, latency=6, bus=None, features=frozenset()): -- 2.30.2