From 0f8722f80c16a649882d02f03d000da946eee737 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 13 May 2017 23:38:20 -0700 Subject: [PATCH] uart: power-on with the right divider for the design (#15) --- src/main/scala/devices/uart/UART.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala index 9b3dfaa..e6349f1 100644 --- a/src/main/scala/devices/uart/UART.scala +++ b/src/main/scala/devices/uart/UART.scala @@ -203,7 +203,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg val rxm = Module(new UARTRx(params)) val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries)) - val divinit = 542 // (62.5MHz / 115200) + val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200 val div = Reg(init = UInt(divinit, uartDivisorBits)) private val stopCountBits = log2Up(uartStopBits) -- 2.30.2