From 0f9ec84b2dd34f91accc08570febec11b6ead781 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 26 Dec 2020 07:29:55 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index d92a37227..28fc21b98 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -39,10 +39,11 @@ registers from 32 to 64 bit). The fundamentals are: -* The Program Counter gains a "Sub Counter" context. -* Vectorisation pauses the PC and runs a loop from 0 to VL-1 - (where VL is Vector Length). This may be thought of as a - "Sub-PC" +* The Program Counter (PC) gains a "Sub Counter" context (Sub-PC) +* Vectorisation pauses the PC and runs a Sub-PC loop from 0 to VL-1 + (where VL is Vector Length) +* The Program Order of "Sub-PC" instructions must be preserved, + just as is expected of instructions ordered by the PC. * Some registers may be "tagged" as Vectors * During the loop, "Vector"-tagged register are incremented by one with each iteration, executing the *same instruction* -- 2.30.2