From 0faf5181dbe2fbe94939023c7146db5c89efc9df Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 20 Apr 2022 18:08:39 +0100 Subject: [PATCH] --- openpower/sv/biginteger.mdwn | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index e0aae5110..a1be1ccb3 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -179,6 +179,26 @@ in `110110`. A corresponding `madded` is proposed for `110010` | ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ | | maddhd | maddhdu | madded | maddld | rsvd | rsvd | msubed | rsvd | +For SVP64 EXTRA register extension, the `RM-1P-3S-1D` format is +used with the additional bit set for determining RS. + +| Field Name | Field bits | Description | +|------------|------------|----------------------------------------| +| Rdest\_EXTRA2 | `10:11` | extends RT (R\*\_EXTRA2 Encoding) | +| Rsrc1\_EXTRA2 | `12:13` | extends RA (R\*\_EXTRA2 Encoding) | +| Rsrc2\_EXTRA2 | `14:15` | extends RB (R\*\_EXTRA2 Encoding) | +| Rsrc3\_EXTRA2 | `16:17` | extends RC (R\*\_EXTRA2 Encoding) | +| EXTRA2_MODE | `18` | used by `msubed` and `madded` for RS | + +When `EXTRA2_MODE` is set to zero, the implicit RS register takes +its Vector/Scalar setting from Rdest_EXTRA2, but all numbering +is offset by VL. *Note that element-width overrides influence this +offset* (see SVP64 [[svp64/appendix]] for full details). + +When `EXTRA2_MODE` is set to one, the implicit RS register is identical +to RC extended to SVP64 numbering, including whether RC is set Scalar or +Vector. + # Appendix see [[appendix]] -- 2.30.2