From 0fb1e68a0ba0dc58e0b97f5bb3f7a46d9b3eae29 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 6 Sep 2012 16:18:11 -0400 Subject: [PATCH] radeonsi: Handle position input parameter for pixel shaders v2 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit v2: - Don't increment ninterp or set any of the have_* flags for TGSI_SEMANTIC_POSITION Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeon/SIInstructions.td | 20 +++++++++++++++++++ src/gallium/drivers/radeon/SIIntrinsics.td | 2 ++ .../drivers/radeonsi/radeonsi_shader.c | 16 ++++++++++++++- src/gallium/drivers/radeonsi/si_state_draw.c | 16 +++++++++++++++ 4 files changed, 53 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 8f9de525340..ffc9537ea70 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -1102,6 +1102,26 @@ def : Pat < imm:$attr, SReg_32:$params) >; +def : Pat < + (int_SI_fs_read_pos 0), + (f32 POS_X_FLOAT) +>; + +def : Pat < + (int_SI_fs_read_pos 1), + (f32 POS_Y_FLOAT) +>; + +def : Pat < + (int_SI_fs_read_pos 2), + (f32 POS_Z_FLOAT) +>; + +def : Pat < + (int_SI_fs_read_pos 3), + (f32 POS_W_FLOAT) +>; + /********** ================== **********/ /********** Intrinsic Patterns **********/ /********** ================== **********/ diff --git a/src/gallium/drivers/radeon/SIIntrinsics.td b/src/gallium/drivers/radeon/SIIntrinsics.td index fbb8dc90fbe..f5c3f76fe27 100644 --- a/src/gallium/drivers/radeon/SIIntrinsics.td +++ b/src/gallium/drivers/radeon/SIIntrinsics.td @@ -34,4 +34,6 @@ let TargetPrefix = "SI", isTarget = 1 in { def int_SI_fs_interp_persp_center : Interp; def int_SI_fs_interp_persp_centroid : Interp; def int_SI_fs_interp_constant : Interp; + + def int_SI_fs_read_pos : Intrinsic <[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>; } diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c index 0994fac6f21..466d5658d5a 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_shader.c +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c @@ -261,6 +261,7 @@ static void declare_input_fs( struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base; struct gallivm_state * gallivm = base->gallivm; + LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context); /* This value is: * [15:0] NewPrimMask (Bit mask for each quad. It is set it the @@ -278,6 +279,20 @@ static void declare_input_fs( /* XXX: Is this the input_index? */ LLVMValueRef attr_number = lp_build_const_int32(gallivm, input_index); + if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) { + for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { + LLVMValueRef args[1]; + unsigned soa_index = + radeon_llvm_reg_index_soa(input_index, chan); + args[0] = lp_build_const_int32(gallivm, chan); + si_shader_ctx->radeon_bld.inputs[soa_index] = + build_intrinsic(base->gallivm->builder, + "llvm.SI.fs.read.pos", input_type, + args, 1, LLVMReadNoneAttribute); + } + return; + } + /* XXX: Handle all possible interpolation modes */ switch (decl->Interp.Interpolate) { case TGSI_INTERPOLATE_COLOR: @@ -332,7 +347,6 @@ static void declare_input_fs( LLVMValueRef args[3]; LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan); unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan); - LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context); args[0] = llvm_chan; args[1] = attr_number; args[2] = params; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 8b43f5a8f7d..c71ad43db24 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -103,6 +103,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s unsigned num_sgprs, num_user_sgprs; int ninterp = 0; boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE; + unsigned fragcoord_interp_mode = 0; unsigned spi_baryc_cntl, spi_ps_input_ena; uint64_t va; @@ -116,6 +117,20 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); for (i = 0; i < shader->shader.ninput; i++) { + if (shader->shader.input[i].name == TGSI_SEMANTIC_POSITION) { + if (shader->shader.input[i].centroid) { + /* fragcoord_interp_mode will be written to + * SPI_BARYC_CNTL.POS_FLOAT_LOCATION + * Possible vaules: + * 0 -> Position = pixel center (default) + * 1 -> Position = pixel centroid + * 2 -> Position = iterated sample number XXX: + * What does this mean? + */ + fragcoord_interp_mode = 1; + } + continue; + } ninterp++; /* XXX: Flat shading hangs the GPU */ if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || @@ -166,6 +181,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s if (have_linear) spi_baryc_cntl |= have_centroid ? S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1); + spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode); si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); spi_ps_input_ena = shader->spi_ps_input_ena; -- 2.30.2