From 0fd1b9df8df192badf287d4d9f31db690276deec Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Feb 2015 21:45:05 +0100 Subject: [PATCH] liteXXX cores: remove redefinition of get_csr_csv --- misoclib/com/liteeth/example_designs/make.py | 13 ++----------- misoclib/mem/litesata/example_designs/make.py | 13 ++----------- misoclib/tools/litescope/example_designs/make.py | 13 ++----------- 3 files changed, 6 insertions(+), 33 deletions(-) diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py index 70694484..44e23284 100644 --- a/misoclib/com/liteeth/example_designs/make.py +++ b/misoclib/com/liteeth/example_designs/make.py @@ -11,18 +11,9 @@ from mibuild import tools from mibuild.xilinx.common import * sys.path.append("../../../../") # Temporary +from misoclib.soc import cpuif from misoclib.com.liteeth.common import * -def get_csr_csv(regions): - r = "" - for name, origin, busword, obj in regions: - if not isinstance(obj, Memory): - for csr in obj: - nr = (csr.size + busword - 1)//busword - r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw") - origin += 4*nr - return r - def _import(default, name): return importlib.import_module(default + "." + name) @@ -128,7 +119,7 @@ System Clk: {} MHz subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = get_csr_csv(soc.cpu_csr_regions) + csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bitstream"]: diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py index 820b872f..ad8ff7df 100644 --- a/misoclib/mem/litesata/example_designs/make.py +++ b/misoclib/mem/litesata/example_designs/make.py @@ -11,18 +11,9 @@ from mibuild import tools from mibuild.xilinx.common import * sys.path.append("../../../../") # Temporary +from misoclib.soc import cpuif from misoclib.mem.litesata.common import * -def get_csr_csv(regions): - r = "" - for name, origin, busword, obj in regions: - if not isinstance(obj, Memory): - for csr in obj: - nr = (csr.size + busword - 1)//busword - r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw") - origin += 4*nr - return r - def _import(default, name): return importlib.import_module(default + "." + name) @@ -134,7 +125,7 @@ BIST: {} subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = get_csr_csv(soc.cpu_csr_regions) + csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-core"]: diff --git a/misoclib/tools/litescope/example_designs/make.py b/misoclib/tools/litescope/example_designs/make.py index e73294f5..64e2c499 100644 --- a/misoclib/tools/litescope/example_designs/make.py +++ b/misoclib/tools/litescope/example_designs/make.py @@ -11,18 +11,9 @@ from mibuild import tools from mibuild.xilinx.common import * sys.path.append("../../../../") # Temporary +from misoclib.soc import cpuif from misoclib.tools.litescope.common import * -def get_csr_csv(regions): - r = "" - for name, origin, busword, obj in regions: - if not isinstance(obj, Memory): - for csr in obj: - nr = (csr.size + busword - 1)//busword - r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw") - origin += 4*nr - return r - def _import(default, name): return importlib.import_module(default + "." + name) @@ -137,7 +128,7 @@ RLE: {} subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = get_csr_csv(soc.cpu_csr_regions) + csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bitstream"]: -- 2.30.2