From 0fd877d2227d3c563b6bf60bcbc205455667a26d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 Apr 2022 12:56:10 +0100 Subject: [PATCH] add name to HyperRAM module so as to be able to pass name to resource bus. this allows multiple HyperRAM modules to be added --- lambdasoc/periph/hyperram.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py index ef7a811..da4e83e 100644 --- a/lambdasoc/periph/hyperram.py +++ b/lambdasoc/periph/hyperram.py @@ -158,10 +158,11 @@ class HyperRAM(Peripheral, Elaboratable): Cypress S27KL0641DABHI020 requires latency=6 """ def __init__(self, *, io, phy_kls, + name=None, latency=6, addr_width=23, # 8 GBytes, per IC bus=None, features=frozenset()): - super().__init__() + super().__init__(name=name) self.n_cs = n_cs = len(io.cs_n) self.cs_bits = cs_bits = n_cs.bit_length()-1 self.io = io @@ -174,7 +175,9 @@ class HyperRAM(Peripheral, Elaboratable): features=features) self.size = 2**addr_width mmap = MemoryMap(addr_width=addr_width, data_width=8) - mmap.add_resource(object(), name="hyperram", size=self.size) + if name is None: + name = "hyperram" + mmap.add_resource(object(), name=name, size=self.size) self.bus.memory_map = mmap # # # -- 2.30.2