From 0fe1f31b9e6a6064b2748b97a971b2b7ccf18337 Mon Sep 17 00:00:00 2001 From: Venkataramanan Kumar Date: Wed, 16 Nov 2011 17:31:38 +0000 Subject: [PATCH] * doc/invoke.texi: Document AMD bdver1 and btver1. From-SVN: r181417 --- gcc/ChangeLog | 4 ++++ gcc/doc/invoke.texi | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7bb2b600804..218681a1edc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2011-11-16 Venkataramanan Kumar + + * doc/invoke.texi: Document AMD bdver1 and btver1. + 2011-11-16 Richard Earnshaw Bernd Schmidt Sebastian Huber diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 1fc44372e32..e58ed1b4ac5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12803,6 +12803,15 @@ Improved versions of k8, opteron and athlon64 with SSE3 instruction set support. AMD Family 10h core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.) +@item bdver1 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit +instruction set extensions.) +@item btver1 +AMD Family 14h core based CPUs with x86-64 instruction set support. (This +supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit +instruction set extensions.) @item winchip-c6 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction set support. -- 2.30.2