From 0ff04a4241c624632205ebcfe57b3693fca621c8 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 8 Dec 2021 19:56:36 -0800 Subject: [PATCH] add parent_pspec everywhere --- src/soc/experiment/alu_hier.py | 4 +- .../test/test_compldst_multi_mmu_fsm.py | 2 +- src/soc/fu/alu/formal/proof_input_stage.py | 2 +- src/soc/fu/alu/formal/proof_main_stage.py | 2 +- src/soc/fu/alu/formal/proof_output_stage.py | 2 +- src/soc/fu/alu/test/test_pipe_caller.py | 4 +- src/soc/fu/branch/formal/proof_input_stage.py | 2 +- src/soc/fu/branch/formal/proof_main_stage.py | 2 +- src/soc/fu/branch/test/test_pipe_caller.py | 4 +- src/soc/fu/compunits/compunits.py | 67 ++++++++++--------- src/soc/fu/cr/formal/proof_main_stage.py | 2 +- src/soc/fu/cr/test/test_pipe_caller.py | 4 +- src/soc/fu/div/pipe_data.py | 22 +++--- src/soc/fu/div/test/helper.py | 3 +- src/soc/fu/div/test/test_pipe_ilang.py | 3 +- .../fu/logical/formal/proof_input_stage.py | 2 +- src/soc/fu/logical/formal/proof_main_stage.py | 2 +- src/soc/fu/logical/test/test_pipe_caller.py | 4 +- .../fu/mmu/test/test_non_production_core.py | 2 +- src/soc/fu/mmu/test/test_pipe_caller.py | 4 +- src/soc/fu/mul/formal/proof_main_stage.py | 2 +- src/soc/fu/mul/test/helper.py | 2 +- src/soc/fu/mul/test/test_pipe_ilang.py | 2 +- src/soc/fu/pipe_data.py | 3 +- .../fu/shift_rot/formal/proof_main_stage.py | 2 +- src/soc/fu/shift_rot/test/test_pipe_caller.py | 4 +- src/soc/fu/spr/formal/proof_main_stage.py | 2 +- src/soc/fu/spr/test/test_pipe_caller.py | 4 +- src/soc/fu/trap/formal/proof_main_stage.py | 2 +- src/soc/fu/trap/test/test_pipe_caller.py | 4 +- 30 files changed, 90 insertions(+), 76 deletions(-) diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index d4ed5aaa..459bbd95 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -218,8 +218,8 @@ class ALUFunctionUnit(FunctionUnitBaseSingle): # class ALUFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.ALU - def __init__(self, idx): - super().__init__(ALUPipeSpec, ALU, 1) + def __init__(self, idx, parent_pspec): + super().__init__(ALUPipeSpec, ALU, 1, parent_pspec) class ALU(Elaboratable): diff --git a/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py b/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py index 5f7ee441..81d21c18 100644 --- a/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py +++ b/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py @@ -139,7 +139,7 @@ class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit): self.mmu = MMU() - pipe_spec = MMUPipeSpec(id_wid=2) + pipe_spec = MMUPipeSpec(id_wid=2, parent_pspec=None) self.fsm = FSMMMUStage(pipe_spec) self.fsm.set_ldst_interface(ldst) diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py index 001c063e..ba65373b 100644 --- a/src/soc/fu/alu/formal/proof_input_stage.py +++ b/src/soc/fu/alu/formal/proof_input_stage.py @@ -32,7 +32,7 @@ class Driver(Elaboratable): recwidth += width comb += p.eq(AnyConst(width)) - pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth) + pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth, parent_pspec=None) m.submodules.dut = dut = ALUInputStage(pspec) a = Signal(64) diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py index 655ca470..de8dc54f 100644 --- a/src/soc/fu/alu/formal/proof_main_stage.py +++ b/src/soc/fu/alu/formal/proof_main_stage.py @@ -37,7 +37,7 @@ class Driver(Elaboratable): width = p.width comb += p.eq(AnyConst(width)) - pspec = ALUPipeSpec(id_wid=2) + pspec = ALUPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = ALUMainStage(pspec) # convenience variables diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py index e20aa1eb..eb6f4571 100644 --- a/src/soc/fu/alu/formal/proof_output_stage.py +++ b/src/soc/fu/alu/formal/proof_output_stage.py @@ -38,7 +38,7 @@ class Driver(Elaboratable): recwidth += width comb += p.eq(AnyConst(width)) - pspec = ALUPipeSpec(id_wid=2) + pspec = ALUPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = ALUOutputStage(pspec) o = Signal(64) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index f40187f4..704fc69a 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -51,7 +51,7 @@ def set_alu_inputs(alu, dec2, sim): class ALUIAllCases(ALUTestCase): def case_ilang(self): - pspec = ALUPipeSpec(id_wid=2) + pspec = ALUPipeSpec(id_wid=2, parent_pspec=None) alu = ALUBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("alu_pipeline.il", "w") as f: @@ -124,7 +124,7 @@ class TestRunner(unittest.TestCase): pdecode, opkls, fn_name) pdecode = pdecode2.dec - pspec = ALUPipeSpec(id_wid=2) + pspec = ALUPipeSpec(id_wid=2, parent_pspec=None) m.submodules.alu = alu = ALUBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py index 79d3c662..739d3b20 100644 --- a/src/soc/fu/branch/formal/proof_input_stage.py +++ b/src/soc/fu/branch/formal/proof_input_stage.py @@ -32,7 +32,7 @@ class Driver(Elaboratable): recwidth += width comb += p.eq(AnyConst(width)) - pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth) + pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth, parent_pspec=None) m.submodules.dut = dut = ALUInputStage(pspec) a = Signal(64) diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py index 5d940b1a..0f58e1c0 100644 --- a/src/soc/fu/branch/formal/proof_main_stage.py +++ b/src/soc/fu/branch/formal/proof_main_stage.py @@ -39,7 +39,7 @@ class Driver(Elaboratable): recwidth += width comb += p.eq(AnyConst(width)) - pspec = BranchPipeSpec(id_wid=2) + pspec = BranchPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = BranchMainStage(pspec) # convenience aliases diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 0b701ae8..794d86da 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -50,7 +50,7 @@ def get_cu_inputs(dec2, sim): class BranchAllCases(BranchTestCase): def case_ilang(self): - pspec = BranchPipeSpec(id_wid=2) + pspec = BranchPipeSpec(id_wid=2, parent_pspec=None) alu = BranchBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("branch_pipeline.il", "w") as f: @@ -70,7 +70,7 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) pdecode = pdecode2.dec - pspec = BranchPipeSpec(id_wid=2) + pspec = BranchPipeSpec(id_wid=2, parent_pspec=None) m.submodules.branch = branch = BranchBasePipe(pspec) comb += branch.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 773bf814..ee9f4981 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -115,9 +115,10 @@ class FunctionUnitBaseSingle(MultiCompUnit): to actually read (and write) the correct register number """ - def __init__(self, speckls, pipekls, idx): + def __init__(self, speckls, pipekls, idx, parent_pspec): alu_name = "alu_%s%d" % (self.fnunit.name.lower(), idx) - pspec = speckls(id_wid=2) # spec (NNNPipeSpec instance) + # spec (NNNPipeSpec instance) + pspec = speckls(id_wid=2, parent_pspec=parent_pspec) opsubset = pspec.opsubsetkls # get the operand subset class regspec = pspec.regspec # get the regspec alu = pipekls(pspec) # create actual NNNBasePipe @@ -154,9 +155,11 @@ class FunctionUnitBaseMulti(ReservationStations2): ideal (it could be a lot neater) but works for now. """ - def __init__(self, speckls, pipekls, num_rows): + def __init__(self, speckls, pipekls, num_rows, parent_pspec): id_wid = num_rows.bit_length() - pspec = speckls(id_wid=id_wid) # spec (NNNPipeSpec instance) + + # spec (NNNPipeSpec instance) + pspec = speckls(id_wid=id_wid, parent_pspec=parent_pspec) opsubset = pspec.opsubsetkls # get the operand subset class regspec = pspec.regspec # get the regspec alu = pipekls(pspec) # create actual NNNBasePipe @@ -191,83 +194,83 @@ class FunctionUnitBaseMulti(ReservationStations2): class ALUFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.ALU - def __init__(self, num_rses): - super().__init__(ALUPipeSpec, ALUBasePipe, num_rses) + def __init__(self, num_rses, parent_pspec): + super().__init__(ALUPipeSpec, ALUBasePipe, num_rses, parent_pspec) # class LogicalFunctionUnit(FunctionUnitBaseSingle): class LogicalFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.LOGICAL - def __init__(self, idx): - super().__init__(LogicalPipeSpec, LogicalBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(LogicalPipeSpec, LogicalBasePipe, idx, parent_pspec) # class CRFunctionUnit(FunctionUnitBaseSingle): class CRFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.CR - def __init__(self, idx): - super().__init__(CRPipeSpec, CRBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(CRPipeSpec, CRBasePipe, idx, parent_pspec) # class BranchFunctionUnit(FunctionUnitBaseSingle): class BranchFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.BRANCH - def __init__(self, idx): - super().__init__(BranchPipeSpec, BranchBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(BranchPipeSpec, BranchBasePipe, idx, parent_pspec) # class ShiftRotFunctionUnit(FunctionUnitBaseSingle): class ShiftRotFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.SHIFT_ROT - def __init__(self, idx): - super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe, idx, parent_pspec) class DivFSMFunctionUnit(FunctionUnitBaseSingle): fnunit = Function.DIV - def __init__(self, idx): - super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx, parent_pspec) class MMUFSMFunctionUnit(FunctionUnitBaseSingle): fnunit = Function.MMU - def __init__(self, idx): - super().__init__(MMUPipeSpec, FSMMMUStage, idx) + def __init__(self, idx, parent_pspec): + super().__init__(MMUPipeSpec, FSMMMUStage, idx, parent_pspec) class DivPipeFunctionUnit(FunctionUnitBaseSingle): fnunit = Function.DIV - def __init__(self, idx): - super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx, parent_pspec) # class MulFunctionUnit(FunctionUnitBaseSingle): class MulFunctionUnit(FunctionUnitBaseMulti): fnunit = Function.MUL - def __init__(self, idx): - super().__init__(MulPipeSpec, MulBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(MulPipeSpec, MulBasePipe, idx, parent_pspec) class TrapFunctionUnit(FunctionUnitBaseSingle): fnunit = Function.TRAP - def __init__(self, idx): - super().__init__(TrapPipeSpec, TrapBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(TrapPipeSpec, TrapBasePipe, idx, parent_pspec) class SPRFunctionUnit(FunctionUnitBaseSingle): fnunit = Function.SPR - def __init__(self, idx): - super().__init__(SPRPipeSpec, SPRBasePipe, idx) + def __init__(self, idx, parent_pspec): + super().__init__(SPRPipeSpec, SPRBasePipe, idx, parent_pspec) # special-case: LD/ST conforms to the CompUnit API but is not a pipeline @@ -275,9 +278,10 @@ class SPRFunctionUnit(FunctionUnitBaseSingle): class LDSTFunctionUnit(LDSTCompUnit): fnunit = Function.LDST - def __init__(self, pi, awid, idx): + def __init__(self, pi, awid, idx, parent_pspec): alu_name = "ldst_%s%d" % (self.fnunit.name.lower(), idx) - pspec = LDSTPipeSpec(id_wid=2) # spec (NNNPipeSpec instance) + # spec (NNNPipeSpec instance) + pspec = LDSTPipeSpec(id_wid=2, parent_pspec=parent_pspec) opsubset = pspec.opsubsetkls # get the operand subset class regspec = pspec.regspec # get the regspec self.opsubsetkls = opsubset @@ -336,13 +340,14 @@ class AllFunctionUnits(Elaboratable): for name, qty in units.items(): kls = alus[name] if issubclass(kls, FunctionUnitBaseMulti): - fu = kls(qty) # create just the one ALU but many "fronts" + # create just the one ALU but many "fronts" + fu = kls(qty, parent_pspec=pspec) self.actual_alus[name] = fu # to be made a module of AllFUs for i in range(qty): self.fus["%s%d" % (name, i)] = fu.cu[i] else: for i in range(qty): - self.fus["%s%d" % (name, i)] = kls(i) + self.fus["%s%d" % (name, i)] = kls(i, parent_pspec=pspec) # debug print for MMU ALU if microwatt_mmu: @@ -354,7 +359,7 @@ class AllFunctionUnits(Elaboratable): return print("pilist", pilist) for i, pi in enumerate(pilist): - self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i) + self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i, pspec) # extract exceptions from any FunctionUnits for easy access self.excs = {} diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py index 0aebcbd7..fa44c4d3 100644 --- a/src/soc/fu/cr/formal/proof_main_stage.py +++ b/src/soc/fu/cr/formal/proof_main_stage.py @@ -37,7 +37,7 @@ class Driver(Elaboratable): recwidth += width comb += p.eq(AnyConst(width)) - pspec = ALUPipeSpec(id_wid=2) + pspec = ALUPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = CRMainStage(pspec) full_cr_in = Signal(32) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 158c89cb..9a92d2d6 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -24,7 +24,7 @@ from openpower.test.cr.cr_cases import CRTestCase class CRIlangCase(TestAccumulatorBase): def case_ilang(self): - pspec = CRPipeSpec(id_wid=2) + pspec = CRPipeSpec(id_wid=2, parent_pspec=None) alu = CRBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("cr_pipeline.il", "w") as f: @@ -144,7 +144,7 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) pdecode = pdecode2.dec - pspec = CRPipeSpec(id_wid=2) + pspec = CRPipeSpec(id_wid=2, parent_pspec=None) m.submodules.alu = alu = CRBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index 4c70fdf1..f79f9806 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -129,8 +129,8 @@ class DivPipeKind(enum.Enum): class DivPipeSpec(CommonPipeSpec): - def __init__(self, id_wid, div_pipe_kind): - super().__init__(id_wid=id_wid) + def __init__(self, id_wid, parent_pspec, div_pipe_kind): + super().__init__(id_wid=id_wid, parent_pspec=parent_pspec) self.div_pipe_kind = div_pipe_kind self.core_config = div_pipe_kind.config.core_config @@ -139,18 +139,24 @@ class DivPipeSpec(CommonPipeSpec): class DivPipeSpecDivPipeCore(DivPipeSpec): - def __init__(self, id_wid): - super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.DivPipeCore) + def __init__(self, id_wid, parent_pspec): + super().__init__(id_wid=id_wid, + parent_pspec=parent_pspec, + div_pipe_kind=DivPipeKind.DivPipeCore) class DivPipeSpecFSMDivCore(DivPipeSpec): - def __init__(self, id_wid): - super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.FSMDivCore) + def __init__(self, id_wid, parent_pspec): + super().__init__(id_wid=id_wid, + parent_pspec=parent_pspec, + div_pipe_kind=DivPipeKind.FSMDivCore) class DivPipeSpecSimOnly(DivPipeSpec): - def __init__(self, id_wid): - super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.SimOnly) + def __init__(self, id_wid, parent_pspec): + super().__init__(id_wid=id_wid, + parent_pspec=parent_pspec, + div_pipe_kind=DivPipeKind.SimOnly) class CoreBaseData(DivInputData): diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py index 80871fd3..18175f12 100644 --- a/src/soc/fu/div/test/helper.py +++ b/src/soc/fu/div/test/helper.py @@ -163,7 +163,8 @@ class DivTestHelper(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind) + pspec = DivPipeSpec( + id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None) m.submodules.alu = alu = DivBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) diff --git a/src/soc/fu/div/test/test_pipe_ilang.py b/src/soc/fu/div/test/test_pipe_ilang.py index a5b34391..a9f0cb27 100644 --- a/src/soc/fu/div/test/test_pipe_ilang.py +++ b/src/soc/fu/div/test/test_pipe_ilang.py @@ -6,7 +6,8 @@ from soc.fu.div.pipeline import DivBasePipe class TestPipeIlang(unittest.TestCase): def write_ilang(self, div_pipe_kind): - pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind) + pspec = DivPipeSpec( + id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None) alu = DivBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f: diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py index b0b70d38..aa9b937d 100644 --- a/src/soc/fu/logical/formal/proof_input_stage.py +++ b/src/soc/fu/logical/formal/proof_input_stage.py @@ -32,7 +32,7 @@ class Driver(Elaboratable): recwidth += width comb += p.eq(AnyConst(width)) - pspec = ALUPipeSpec(id_wid=2) + pspec = ALUPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = ALUInputStage(pspec) a = Signal(64) diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py index deac8b75..87d87283 100644 --- a/src/soc/fu/logical/formal/proof_main_stage.py +++ b/src/soc/fu/logical/formal/proof_main_stage.py @@ -47,7 +47,7 @@ class Driver(Elaboratable): width = p.width comb += p.eq(AnyConst(width)) - pspec = ALUPipeSpec(id_wid=2) + pspec = ALUPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = LogicalMainStage(pspec) # convenience variables diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index cd26976e..5ecbe230 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -51,7 +51,7 @@ def set_alu_inputs(alu, dec2, sim): class LogicalIlangCase(TestAccumulatorBase): def case_ilang(self): - pspec = LogicalPipeSpec(id_wid=2) + pspec = LogicalPipeSpec(id_wid=2, parent_pspec=None) alu = LogicalBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("logical_pipeline.il", "w") as f: @@ -116,7 +116,7 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - pspec = LogicalPipeSpec(id_wid=2) + pspec = LogicalPipeSpec(id_wid=2, parent_pspec=None) m.submodules.alu = alu = LogicalBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) diff --git a/src/soc/fu/mmu/test/test_non_production_core.py b/src/soc/fu/mmu/test/test_non_production_core.py index a9957990..e234ac22 100644 --- a/src/soc/fu/mmu/test/test_non_production_core.py +++ b/src/soc/fu/mmu/test/test_non_production_core.py @@ -50,7 +50,7 @@ class MMUTestCase(TestAccumulatorBase): initial_regs, initial_sprs) # def case_ilang(self): - # pspec = SPRPipeSpec(id_wid=2) + # pspec = SPRPipeSpec(id_wid=2, parent_pspec=None) # alu = SPRBasePipe(pspec) # vl = rtlil.convert(alu, ports=alu.ports()) # with open("trap_pipeline.il", "w") as f: diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index 70c853eb..8f36cfd8 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -73,7 +73,7 @@ def check_fsm_outputs(fsm, pdecode2, sim, code): class MMUIlangCase(TestAccumulatorBase): # def case_ilang(self): - # pspec = SPRPipeSpec(id_wid=2) + # pspec = SPRPipeSpec(id_wid=2, parent_pspec=None) # alu = SPRBasePipe(pspec) # vl = rtlil.convert(alu, ports=alu.ports()) # with open("trap_pipeline.il", "w") as f: @@ -220,7 +220,7 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - pipe_spec = MMUPipeSpec(id_wid=2) + pipe_spec = MMUPipeSpec(id_wid=2, parent_pspec=None) ldst = LoadStore1(pspec) fsm = FSMMMUStage(pipe_spec) fsm.set_ldst_interface(ldst) diff --git a/src/soc/fu/mul/formal/proof_main_stage.py b/src/soc/fu/mul/formal/proof_main_stage.py index 0b68c144..a7829460 100644 --- a/src/soc/fu/mul/formal/proof_main_stage.py +++ b/src/soc/fu/mul/formal/proof_main_stage.py @@ -84,7 +84,7 @@ class Driver(Elaboratable): # set up the mul stages. do not add them to m.submodules, this # is handled by StageChain.setup(). - pspec = MulPipeSpec(id_wid=2) + pspec = MulPipeSpec(id_wid=2, parent_pspec=None) pipe1 = MulMainStage1(pspec) pipe2 = MulMainStage2(pspec) pipe3 = MulMainStage3(pspec) diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py index bb9d8d84..4528f408 100644 --- a/src/soc/fu/mul/test/helper.py +++ b/src/soc/fu/mul/test/helper.py @@ -146,7 +146,7 @@ class MulTestHelper(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) pdecode = pdecode2.dec - pspec = MulPipeSpec(id_wid=2) + pspec = MulPipeSpec(id_wid=2, parent_pspec=None) m.submodules.alu = alu = MulBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) diff --git a/src/soc/fu/mul/test/test_pipe_ilang.py b/src/soc/fu/mul/test/test_pipe_ilang.py index 22af35ba..c6ffabeb 100644 --- a/src/soc/fu/mul/test/test_pipe_ilang.py +++ b/src/soc/fu/mul/test/test_pipe_ilang.py @@ -6,7 +6,7 @@ from soc.fu.mul.pipeline import MulBasePipe class TestPipeIlang(unittest.TestCase): def write_ilang(self): - pspec = MulPipeSpec(id_wid=2) + pspec = MulPipeSpec(id_wid=2, parent_pspec=None) alu = MulBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("mul_pipeline.il", "w") as f: diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py index b43244b3..d48cf4c3 100644 --- a/src/soc/fu/pipe_data.py +++ b/src/soc/fu/pipe_data.py @@ -75,13 +75,14 @@ class CommonPipeSpec: see README.md for explanation of members. """ - def __init__(self, id_wid): + def __init__(self, id_wid, parent_pspec): self.pipekls = SimpleHandshakeRedir self.id_wid = id_wid self.opkls = lambda _: self.opsubsetkls() self.op_wid = get_rec_width(self.opkls(None)) # hmm.. self.stage = None self.draft_bitmanip = False + self.parent_pspec = parent_pspec def get_pspec_draft_bitmanip(pspec): diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index 4528de0a..74b4d7db 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -54,7 +54,7 @@ class Driver(Elaboratable): comb += rec.is_signed.eq(AnyConst(rec.is_signed.width)) comb += rec.insn.eq(AnyConst(rec.insn.width)) - pspec = ShiftRotPipeSpec(id_wid=2) + pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = ShiftRotMainStage(pspec) # convenience variables diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index 00bb3262..3bab8081 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -70,7 +70,7 @@ def set_alu_inputs(alu, dec2, sim): class ShiftRotIlangCase(TestAccumulatorBase): def case_ilang(self): - pspec = ShiftRotPipeSpec(id_wid=2) + pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=None) pspec.draft_bitmanip = True alu = ShiftRotBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) @@ -137,7 +137,7 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) pdecode = pdecode2.dec - pspec = ShiftRotPipeSpec(id_wid=2) + pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=None) pspec.draft_bitmanip = True m.submodules.alu = alu = ShiftRotBasePipe(pspec) diff --git a/src/soc/fu/spr/formal/proof_main_stage.py b/src/soc/fu/spr/formal/proof_main_stage.py index 5a1f6894..db9f86a8 100644 --- a/src/soc/fu/spr/formal/proof_main_stage.py +++ b/src/soc/fu/spr/formal/proof_main_stage.py @@ -48,7 +48,7 @@ class Driver(Elaboratable): width = p.width comb += p.eq(AnyConst(width)) - pspec = SPRPipeSpec(id_wid=2) + pspec = SPRPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = SPRMainStage(pspec) # frequently used aliases diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index d6aa34ea..894212bc 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -61,7 +61,7 @@ def set_alu_inputs(alu, dec2, sim): class SPRIlangCase(TestAccumulatorBase): def case_ilang(self): - pspec = SPRPipeSpec(id_wid=2) + pspec = SPRPipeSpec(id_wid=2, parent_pspec=None) alu = SPRBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("trap_pipeline.il", "w") as f: @@ -139,7 +139,7 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - pspec = SPRPipeSpec(id_wid=2) + pspec = SPRPipeSpec(id_wid=2, parent_pspec=None) m.submodules.alu = alu = SPRBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py index c00a3fbf..b94f7e73 100644 --- a/src/soc/fu/trap/formal/proof_main_stage.py +++ b/src/soc/fu/trap/formal/proof_main_stage.py @@ -37,7 +37,7 @@ class Driver(Elaboratable): comb = m.d.comb rec = CompTrapOpSubset() - pspec = TrapPipeSpec(id_wid=2) + pspec = TrapPipeSpec(id_wid=2, parent_pspec=None) m.submodules.dut = dut = TrapMainStage(pspec) diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 5b52860a..428d3e72 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -66,7 +66,7 @@ def set_alu_inputs(alu, dec2, sim): class TrapIlangCase(TestAccumulatorBase): def case_ilang(self): - pspec = TrapPipeSpec(id_wid=2) + pspec = TrapPipeSpec(id_wid=2, parent_pspec=None) alu = TrapBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("trap_pipeline.il", "w") as f: @@ -87,7 +87,7 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - pspec = TrapPipeSpec(id_wid=2) + pspec = TrapPipeSpec(id_wid=2, parent_pspec=None) m.submodules.alu = alu = TrapBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) -- 2.30.2