From 0ffc4dca8ed0e0305a3499164dd8b1913d6aa48e Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Tue, 13 Apr 1999 16:15:46 +0200 Subject: [PATCH] Jan Hubicka Jan Hubicka * i386.md: Do not output mov %0,reg on AMD K6. From-SVN: r26406 --- gcc/ChangeLog | 4 ++++ gcc/config/i386/i386.md | 18 ++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ee6ed839e91..9cdc3f422e0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +Tue Apr 13 14:14:06 1999 Jan Hubicka + + * i386.md: Do not output mov %0,reg on AMD K6. + Tue Apr 13 12:14:07 1999 Dave Brolley * cppinit.c (cpp_start_read): Fix buffer overwrite. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 8eade3ebb58..7e143ac197c 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -983,8 +983,13 @@ "* { rtx link; - if ((ix86_cpu != PROCESSOR_K6 || optimize_size) - && operands[1] == const0_rtx && REG_P (operands[0])) + + /* Use of xor was disabled for AMD K6 as recommended by the Optimization + Manual. My test shows, that this generally hurts the performance, because + mov is longer and takes longer to decode and decoding is the main + bottleneck of K6 when executing GCC code. */ + + if (operands[1] == const0_rtx && REG_P (operands[0])) return AS2 (xor%L0,%0,%0); if (operands[1] == const1_rtx @@ -1111,8 +1116,13 @@ "* { rtx link; - if ((ix86_cpu != PROCESSOR_K6 || optimize_size) - && operands[1] == const0_rtx && REG_P (operands[0])) + + /* Use of xor was disabled for AMD K6 as recommended by the Optimization + Manual. My test shows, that this generally hurts the performance, because + mov is longer and takes longer to decode and decoding is the main + bottleneck of K6 when executing GCC code. */ + + if (operands[1] == const0_rtx && REG_P (operands[0])) return AS2 (xor%W0,%0,%0); if (operands[1] == const1_rtx -- 2.30.2