From 100616cabe4d47f6a2eb9e25ea976c8eceddfd8d Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 5 Sep 2021 17:30:39 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 1baca3102..e52d3e075 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -41,9 +41,18 @@ a number of different modes: * fixed stride (contiguous sequence with no gaps) aka "unit" stride * element strided (sequential but regularly offset, with gaps) * vector indexed (vector of base addresses and vector of offsets) -* fail-first on the same (where it makes sense to do so) +* Speculative fail-first (where it makes sense to do so) * Structure Packing (covered in SV by [[sv/remap]]). +Also included in SVP64 LD/ST is both signed and unsigned Saturation, +as well as Eement-width overrides and Twin-Predication. + +*Missing* from Scalar Power ISA v3.0B is a scalar [[mv.x] instruction +on top of which any good Vector ISA provides Vector Scatter-Gather. +Due to the way that SVP64 is desigbed, this needs to be added separately +(to Scalar Power ISA) before the +Vectorised variant can also be made available. + # Vectorisation of Scalar Power ISA v3.0B OpenPOWER Load/Store operations may be seen from [[isa/fixedload]] and -- 2.30.2