From 101682631355dd0917e78760a61bdd566cf0fbf8 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 24 Jan 2021 13:33:26 +0000 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 16742d944..3fcb519eb 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -281,6 +281,21 @@ LD/ST, will give that same capability, with far more flexibility. # notes from lxo +this section covers assembly notation for the immediate and indexed LD/ST. +the summary is that in immediate mode for LD it is not clear that if the +destination register is Vectorised `RT.v` but the source `imm(RA)` is scalar +the memory being read is *still a vector load*. + +This anomaly is made clear with the following notation: + + sv.ld RT.v, imm(RA).v + +The following notation, although technically correct due to being implicitly identical to the above, is prohibited and is a syntax error: + + sv.ld RT.v, imm(RA) + +Notes taken from IRC conversation + sv.ld r#.v, ofst(r#).v -> the whole vector is at ofst+r# sv.ld r#.v, ofst(r#.v) -> r# is a vector of addresses similarly sv.ldx r#.v, r#, r#.v -> whole vector at r#+r# -- 2.30.2