From 1032bacb081c79b104cc31431c6c081a0773db2e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 5 Dec 2021 13:38:19 +0000 Subject: [PATCH] fix icache row store issue --- src/soc/experiment/dcache.py | 2 +- src/soc/experiment/icache.py | 19 ++++++------------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 0b5950ce..a5548cfb 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1694,7 +1694,7 @@ cache_tags(r1.store_index)((i + 1) * TAG_WIDTH - 1 downto i * TAG_WIDTH) <= # deal with litex not doing wishbone pipeline mode # XXX in wrong way. FIFOs are needed in the SRAM test - # so that stb/ack match up + # so that stb/ack match up. same thing done in icache.py comb += self.bus.stall.eq(self.bus.cyc & ~self.bus.ack) # Wire up wishbone request latch out of stage 1 diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 5936cbe9..f8477562 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -676,12 +676,8 @@ class ICache(Elaboratable): # Calculate the next row address rarange = Signal(LINE_OFF_BITS - ROW_OFF_BITS) - comb += rarange.eq( - r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS] + 1 - ) - sync += r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS].eq( - rarange - ) + comb += rarange.eq(r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS] + 1) + sync += r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS].eq(rarange) sync += Display("RARANGE r.req_adr:%x rarange:%x " "stbs_zero:%x stbs_done:%x", r.req_adr, rarange, stbs_zero, stbs_done) @@ -695,8 +691,7 @@ class ICache(Elaboratable): sync += r.rows_valid[r.store_row % ROW_PER_LINE].eq(1) # Check for completion - with m.If(stbs_done & - is_last_row(r.store_row, r.end_row_ix)): + with m.If(stbs_done & is_last_row(r.store_row, r.end_row_ix)): # Complete wishbone cycle sync += r.wb.cyc.eq(0) # be nice, clear addr @@ -712,11 +707,9 @@ class ICache(Elaboratable): sync += r.state.eq(State.IDLE) - # not completed, move on to next request in row - with m.Else(): - # Increment store row counter - sync += r.store_row.eq(next_row(r.store_row)) - + # move on to next request in row + # Increment store row counter + sync += r.store_row.eq(next_row(r.store_row)) # Cache miss/reload synchronous machine def icache_miss(self, m, cache_valid_bits, r, req_is_miss, -- 2.30.2