From 10670e22acf82a3ea9259bf54e74ea095c6c8851 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 17 May 2019 22:21:57 +0200
Subject: [PATCH] soc/cores/minerva: update to latest

---
 litex/soc/cores/cpu/minerva/core.py | 44 ++++++++++++++---------------
 litex/soc/cores/cpu/minerva/verilog |  2 +-
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 73279aba..219ddc94 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -55,30 +55,30 @@ class Minerva(Module):
             i_external_interrupt=self.interrupt,
 
             # ibus
-            o_ibus_stb=self.ibus.stb,
-            o_ibus_cyc=self.ibus.cyc,
-            o_ibus_cti=self.ibus.cti,
-            o_ibus_bte=self.ibus.bte,
-            o_ibus_we=self.ibus.we,
-            o_ibus_adr=self.ibus.adr,
-            o_ibus_dat_w=self.ibus.dat_w,
-            o_ibus_sel=self.ibus.sel,
-            i_ibus_ack=self.ibus.ack,
-            i_ibus_err=self.ibus.err,
-            i_ibus_dat_r=self.ibus.dat_r,
+            o_ibus__stb=self.ibus.stb,
+            o_ibus__cyc=self.ibus.cyc,
+            o_ibus__cti=self.ibus.cti,
+            o_ibus__bte=self.ibus.bte,
+            o_ibus__we=self.ibus.we,
+            o_ibus__adr=self.ibus.adr,
+            o_ibus__dat_w=self.ibus.dat_w,
+            o_ibus__sel=self.ibus.sel,
+            i_ibus__ack=self.ibus.ack,
+            i_ibus__err=self.ibus.err,
+            i_ibus__dat_r=self.ibus.dat_r,
 
             # dbus
-            o_dbus_stb=self.dbus.stb,
-            o_dbus_cyc=self.dbus.cyc,
-            o_dbus_cti=self.dbus.cti,
-            o_dbus_bte=self.dbus.bte,
-            o_dbus_we=self.dbus.we,
-            o_dbus_adr=self.dbus.adr,
-            o_dbus_dat_w=self.dbus.dat_w,
-            o_dbus_sel=self.dbus.sel,
-            i_dbus_ack=self.dbus.ack,
-            i_dbus_err=self.dbus.err,
-            i_dbus_dat_r=self.dbus.dat_r,
+            o_dbus__stb=self.dbus.stb,
+            o_dbus__cyc=self.dbus.cyc,
+            o_dbus__cti=self.dbus.cti,
+            o_dbus__bte=self.dbus.bte,
+            o_dbus__we=self.dbus.we,
+            o_dbus__adr=self.dbus.adr,
+            o_dbus__dat_w=self.dbus.dat_w,
+            o_dbus__sel=self.dbus.sel,
+            i_dbus__ack=self.dbus.ack,
+            i_dbus__err=self.dbus.err,
+            i_dbus__dat_r=self.dbus.dat_r,
         )
 
         # add verilog sources
diff --git a/litex/soc/cores/cpu/minerva/verilog b/litex/soc/cores/cpu/minerva/verilog
index 297db8ad..afa72e04 160000
--- a/litex/soc/cores/cpu/minerva/verilog
+++ b/litex/soc/cores/cpu/minerva/verilog
@@ -1 +1 @@
-Subproject commit 297db8adfed0671afd6114f8ff3c18c9434e4686
+Subproject commit afa72e04353831fba3c3df43f4491272994e6af2
-- 
2.30.2