From 106817db3ac8aadce394b6902058d8bbffdc859b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 19 Oct 2023 11:22:41 +0100 Subject: [PATCH] add fixedstoreshift.mdwn as an initial copy of fixedstore.mdwn only indexed instructions, to be edited to add "sm" (shift amount) https://bugs.libre-soc.org/show_bug.cgi?id=1055 --- openpower/isa/fixedstoreshift.mdwn | 305 +++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+) create mode 100644 openpower/isa/fixedstoreshift.mdwn diff --git a/openpower/isa/fixedstoreshift.mdwn b/openpower/isa/fixedstoreshift.mdwn new file mode 100644 index 00000000..6b47b8f3 --- /dev/null +++ b/openpower/isa/fixedstoreshift.mdwn @@ -0,0 +1,305 @@ + + + + + + + + + + + + + + + + +# Store Byte Indexed + +X-Form + +* stbx RS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1] + +Description: + + Let the effective address (EA) be the sum + (RA|0)+ (RB). RS [56:63] are stored into the byte in stor- + age addressed by EA. + +Special Registers Altered: + + None + +# Store Byte with Update Indexed + +X-Form + +* stbux RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1] + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA)+ (RB). + RS[56:63] are stored into the byte in storage addressed + by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Store Halfword Indexed + +X-Form + +* sthx RS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1] + +Description: + + Let the effective address (EA) be the sum + (RA|0)+ (RB). RS[48:63] are stored into the halfword in + storage addressed by EA. + +Special Registers Altered: + + None + +# Store Halfword with Update Indexed + +X-Form + +* sthux RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1] + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA)+ (RB). + RS[48:63] are stored into the halfword in storage + addressed by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Store Word Indexed + +X-Form + +* stwx RS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1] + +Description: + + Let the effective address (EA) be the sum + (RA|0)+ (RB). RS[32:63] are stored into the word in stor- + age addressed by EA. + +Special Registers Altered: + + None + +# Store Word with Update Indexed + +X-Form + +* stwux RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1] + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA)+ (RB). + RS[32:63] are stored into the word in storage addressed + by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + + + + + +# Store Doubleword Indexed + +X-Form + +* stdx RS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 8) <- (RS) + +Description: + + Let the effective address (EA) be the sum + (RA|0)+ (RB). (RS) is stored into the doubleword in + storage addressed by EA. + +Special Registers Altered: + + None + +# Store Doubleword with Update Indexed + +X-Form + +* stdux RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + MEM(EA, 8) <- (RS) + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA)+ (RB). + (RS) is stored into the doubleword in storage + addressed by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + + + + +# Store Halfword Byte-Reverse Indexed + +X-Form + +* sthbrx RS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55] + +Description: + + Let the effective address (EA) be the sum + (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the + halfword in storage addressed by EA. (RS) 48:55 are + stored into bits 8:15 of the halfword in storage + addressed by EA. + +Special Registers Altered: + + None + +# Store Word Byte-Reverse Indexed + +X-Form + +* stwbrx RS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47] + ||(RS)[32:39]) + +Description: + + Let the effective address (EA) be the sum + (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the + word in storage addressed by EA. (RS) [48:55] are stored + into bits 8:15 of the word in storage addressed by EA. + (RS)[40:47] are stored into bits 16:23 of the word in stor- + age addressed by EA. (RS) [32:39] are stored into bits + 24:31 of the word in storage addressed by EA. + +Special Registers Altered: + + None + + + +# Store Doubleword Byte-Reverse Indexed + +X-Form + +* stdbrx RS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55] + || (RS)[40:47] || (RS)[32:39] + || (RS)[24:31] || (RS)[16:23] + || (RS)[8:15] || (RS)[0:7]) + +Description: + + Let the effective address (EA) be the sum + (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the + doubleword in storage addressed by EA. (RS) [48:55] are + stored into bits 8:15 of the doubleword in storage + addressed by EA. (RS) [40:47] are stored into bits 16:23 of + the doubleword in storage addressed by EA. (RS) [32:39] + are stored into bits 23:31 of the doubleword in storage + addressed by EA. (RS) [24:31] are stored into bits 32:39 of + the doubleword in storage addressed by EA. (RS) [16:23] + are stored into bits 40:47 of the doubleword in storage + addressed by EA. (RS)[8:15] are stored into bits 48:55 of + the doubleword in storage addressed by EA. (RS) [0:7] + are stored into bits 56:63 of the doubleword in storage + addressed by EA. + +Special Registers Altered: + + None + + -- 2.30.2