From 107f03fd4bdef5eee9b6436c3084c50c3518e07a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 18 Dec 2011 21:47:48 +0100 Subject: [PATCH] Remove uses of declare_signal --- migen/bank/csrgen.py | 10 +++---- migen/bus/wishbone.py | 21 +++++++-------- migen/corelogic/divider.py | 50 +++++++++++++++++------------------ migen/corelogic/roundrobin.py | 4 +-- migen/corelogic/timeline.py | 17 ++++++------ 5 files changed, 49 insertions(+), 53 deletions(-) diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index acd0d7dc..366e6bd9 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -7,13 +7,13 @@ class Bank: self.description = description self.address = address self.interface = Slave() - declare_signal(self, "_sel") def get_fragment(self): comb = [] sync = [] - comb.append(self._sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5)))) + sel = Signal() + comb.append(sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5)))) nregs = len(self.description) nbits = bits_for(nregs-1) @@ -33,11 +33,11 @@ class Bank: bwcases.append(bwra) else: comb.append(reg.dev_r.eq(self.interface.d_i[:reg.raw.width])) - comb.append(reg.dev_re.eq(self._sel & \ + comb.append(reg.dev_re.eq(sel & \ self.interface.we_i & \ (self.interface.a_i[:nbits] == Constant(i, BV(nbits))))) if bwcases: - sync.append(If(self._sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases))) + sync.append(If(sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases))) # Bus reads brcases = [] @@ -63,7 +63,7 @@ class Bank: brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(reg.dev_w)]) if brcases: sync.append(self.interface.d_o.eq(Constant(0, BV(8)))) - sync.append(If(self._sel, Case(self.interface.a_i[:nbits], *brcases))) + sync.append(If(sel, Case(self.interface.a_i[:nbits], *brcases))) else: comb.append(self.interface.d_o.eq(Constant(0, BV(8)))) diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py index 8fc48004..4cae9fd4 100644 --- a/migen/bus/wishbone.py +++ b/migen/bus/wishbone.py @@ -1,5 +1,3 @@ -from functools import partial - from migen.fhdl.structure import * from migen.corelogic import roundrobin, multimux from migen.bus.simple import Simple, get_sig_name @@ -83,27 +81,26 @@ class Decoder: else: return x self.addresses = list(map(mkconst, addresses)) - - ns = len(self.slaves) - d = partial(declare_signal, self) - d("_slave_sel", BV(ns)) - d("_slave_sel_r", BV(ns)) def get_fragment(self): comb = [] sync = [] + ns = len(self.slaves) + slave_sel = Signal(BV(ns)) + slave_sel_r = Signal(BV(ns)) + # decode slave addresses i = 0 hi = self.master.adr_o.bv.width - self.offset for addr in self.addresses: - comb.append(self._slave_sel[i].eq( + comb.append(slave_sel[i].eq( self.master.adr_o[hi-addr.bv.width:hi] == addr)) i += 1 if self.register: - sync.append(self._slave_sel_r.eq(self._slave_sel)) + sync.append(slave_sel_r.eq(slave_sel)) else: - comb.append(self._slave_sel_r.eq(self._slave_sel)) + comb.append(slave_sel_r.eq(slave_sel)) # connect master->slaves signals except cyc m2s_names = [(get_sig_name(x, False), get_sig_name(x, True)) @@ -114,7 +111,7 @@ class Decoder: # combine cyc with slave selection signals i = 0 for slave in self.slaves: - comb.append(slave[1].cyc_i.eq(self.master.cyc_o & self._slave_sel[i])) + comb.append(slave[1].cyc_i.eq(self.master.cyc_o & slave_sel[i])) i += 1 # generate master ack (resp. err) by ORing all slave acks (resp. errs) @@ -130,7 +127,7 @@ class Decoder: i = 0 datav = Constant(0, self.master.dat_i.bv) for slave in self.slaves: - datav = datav | (Replicate(self._slave_sel_r[i], self.master.dat_i.bv.width) & slave[1].dat_o) + datav = datav | (Replicate(slave_sel_r[i], self.master.dat_i.bv.width) & slave[1].dat_o) i += 1 comb.append(self.master.dat_i.eq(datav)) diff --git a/migen/corelogic/divider.py b/migen/corelogic/divider.py index 880074af..f411b92f 100644 --- a/migen/corelogic/divider.py +++ b/migen/corelogic/divider.py @@ -1,44 +1,42 @@ -from functools import partial - from migen.fhdl.structure import * class Inst: def __init__(self, w): self.w = w - d = partial(declare_signal, self) - - d("start_i") - d("dividend_i", BV(w)) - d("divisor_i", BV(w)) - d("ready_o") - d("quotient_o", BV(w)) - d("remainder_o", BV(w)) - - d("_qr", BV(2*w)) - d("_counter", BV(bits_for(w))) - d("_divisor_r", BV(w)) - d("_diff", BV(w+1)) + start_i = Signal() + dividend_i = Signal(BV(w)) + divisor_i = Signal(BV(w)) + ready_o = Signal() + quotient_o = Signal(BV(w)) + remainder_o = Signal(BV(w)) def get_fragment(self): + w = self.w + + qr = Signal(BV(2*w)) + counter = Signal(BV(bits_for(w))) + divisor_r = Signal(BV(w)) + diff = Signal(BV(w+1)) + comb = [ - self.quotient_o.eq(self._qr[:self.w]), - self.remainder_o.eq(self._qr[self.w:]), - self.ready_o.eq(self._counter == Constant(0, self._counter.bv)), - self._diff.eq(self.remainder_o - self._divisor_r) + self.quotient_o.eq(qr[:w]), + self.remainder_o.eq(qr[w:]), + self.ready_o.eq(counter == Constant(0, counter.bv)), + diff.eq(self.remainder_o - divisor_r) ] sync = [ If(self.start_i, - self._counter.eq(self.w), - self._qr.eq(self.dividend_i), - self._divisor_r.eq(self.divisor_i) + counter.eq(w), + qr.eq(self.dividend_i), + divisor_r.eq(self.divisor_i) ).Elif(~self.ready_o, - If(self._diff[self.w], - self._qr.eq(Cat(0, self._qr[:2*self.w-1])) + If(diff[w], + qr.eq(Cat(0, qr[:2*w-1])) ).Else( - self._qr.eq(Cat(1, self._qr[:self.w-1], self._diff[:self.w])) + qr.eq(Cat(1, qr[:w-1], diff[:w])) ), - self._counter.eq(self._counter - Constant(1, self._counter.bv)) + counter.eq(counter - Constant(1, counter.bv)) ) ] return Fragment(comb, sync) diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py index 8926e987..850fbd2f 100644 --- a/migen/corelogic/roundrobin.py +++ b/migen/corelogic/roundrobin.py @@ -4,8 +4,8 @@ class Inst: def __init__(self, n): self.n = n self.bn = bits_for(self.n-1) - declare_signal(self, "request", BV(self.n)) - declare_signal(self, "grant", BV(self.bn)) + request = Signal(BV(self.n)) + grant = Signal(BV(self.bn)) def get_fragment(self): cases = [] diff --git a/migen/corelogic/timeline.py b/migen/corelogic/timeline.py index efe09a18..f47e188f 100644 --- a/migen/corelogic/timeline.py +++ b/migen/corelogic/timeline.py @@ -5,27 +5,28 @@ class Inst: self.trigger = trigger self.events = events self.lastevent = max([e[0] for e in events]) - declare_signal(self, "_counter", BV(bits_for(self.lastevent))) def get_fragment(self): - counterlogic = If(self._counter != Constant(0, self._counter.bv), - self._counter.eq(self._counter + Constant(1, self._counter.bv)) + counter = Signal(BV(bits_for(self.lastevent))) + + counterlogic = If(counter != Constant(0, counter.bv), + counter.eq(counter + Constant(1, counter.bv)) ).Elif(self.trigger, - self._counter.eq(Constant(1, self._counter.bv)) + counter.eq(Constant(1, counter.bv)) ) # insert counter reset if it doesn't automatically overflow # (test if self.lastevent+1 is a power of 2) if (self.lastevent & (self.lastevent + 1)) != 0: - counterlogic = If(self._counter == self.lastevent, - self._counter.eq(Constant(0, self._counter.bv)) + counterlogic = If(counter == self.lastevent, + counter.eq(Constant(0, counter.bv)) ).Else( counterlogic ) def get_cond(e): if e[0] == 0: - return self.trigger & (self._counter == Constant(0, self._counter.bv)) + return self.trigger & (counter == Constant(0, counter.bv)) else: - return self._counter == Constant(e[0], self._counter.bv) + return counter == Constant(e[0], counter.bv) sync = [If(get_cond(e), *e[1]) for e in self.events] sync.append(counterlogic) return Fragment(sync=sync) -- 2.30.2