From 10a883113b6d5657efeb9d3eedef1a13f97185f3 Mon Sep 17 00:00:00 2001 From: Terry Guo Date: Wed, 17 Apr 2013 06:24:48 +0000 Subject: [PATCH] * config/arm/cortex-m4.md: Add a new bypass. From-SVN: r198021 --- gcc/ChangeLog | 4 ++++ gcc/config/arm/cortex-m4.md | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3ccbb0c1ea2..a2408e6e7dd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2013-04-17 Terry Guo + + * config/arm/cortex-m4.md: Add a new bypass. + 2013-04-16 Naveen H.S * config/aarch64/aarch64.md (*adds__multp2): diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 187867bfebc..47b03644f73 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -84,6 +84,10 @@ (eq_attr "type" "store4")) "cortex_m4_ex*5") +(define_bypass 1 "cortex_m4_load1" + "cortex_m4_store1_1,cortex_m4_store1_2" + "arm_no_early_store_addr_dep") + ;; If the address of load or store depends on the result of the preceding ;; instruction, the latency is increased by one. -- 2.30.2