From 10bfe16f97e9d25a748c563c14802a7c29b4f546 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Thu, 24 Aug 2017 19:19:50 +0200 Subject: [PATCH] target-supports.exp: Group together target-dependant checks. * lib/target-supports.exp: Group together target-dependant checks. From-SVN: r251338 --- gcc/testsuite/ChangeLog | 4 + gcc/testsuite/lib/target-supports.exp | 314 +++++++++++++------------- 2 files changed, 165 insertions(+), 153 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1720a89b2e3..908212fcf03 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-08-24 Uros Bizjak + + * lib/target-supports.exp: Group together target-dependant checks. + 2017-08-24 Bin Cheng PR tree-optimization/81913 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 547fe7a2ff2..3ddc92ee273 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1571,30 +1571,6 @@ proc check_linker_plugin_available { } { } "-flto -fuse-linker-plugin"] } -# Return 1 if the target supports executing 750CL paired-single instructions, 0 -# otherwise. Cache the result. - -proc check_750cl_hw_available { } { - return [check_cached_effective_target 750cl_hw_available { - # If this is not the right target then we can skip the test. - if { ![istarget powerpc-*paired*] } { - expr 0 - } else { - check_runtime_nocache 750cl_hw_available { - int main() - { - #ifdef __MACH__ - asm volatile ("ps_mul v0,v0,v0"); - #else - asm volatile ("ps_mul 0,0,0"); - #endif - return 0; - } - } "-mpaired" - } - }] -} - # Return 1 if the target OS supports running SSE executables, 0 # otherwise. Cache the result. @@ -1635,7 +1611,7 @@ proc check_avx_os_support_available { } { unsigned int eax, edx; asm ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0)); - return (eax & 6) != 6; + return (eax & 0x06) != 0x06; } } "" } @@ -1679,92 +1655,16 @@ proc check_sse_hw_available { } { int main () { unsigned int eax, ebx, ecx, edx; - if (__get_cpuid (1, &eax, &ebx, &ecx, &edx)) - return !(edx & bit_SSE); - return 1; - } - } "" - } - }] -} - -# Return 1 if the target supports executing MIPS Paired-Single instructions, -# 0 otherwise. Cache the result. - -proc check_mpaired_single_hw_available { } { - return [check_cached_effective_target mpaired_single_hw_available { - # If this is not the right target then we can skip the test. - if { !([istarget mips*-*-*]) } { - expr 0 - } else { - check_runtime_nocache mpaired_single_hw_available { - int main() - { - asm volatile ("pll.ps $f2,$f4,$f6"); - return 0; - } - } "" - } - }] -} - -# Return 1 if the target supports executing Loongson vector instructions, -# 0 otherwise. Cache the result. + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 1; -proc check_mips_loongson_hw_available { } { - return [check_cached_effective_target mips_loongson_hw_available { - # If this is not the right target then we can skip the test. - if { !([istarget mips*-*-*]) } { - expr 0 - } else { - check_runtime_nocache mips_loongson_hw_available { - #include - int main() - { - asm volatile ("paddw $f2,$f4,$f6"); - return 0; - } + return !(edx & bit_SSE); + } } "" } }] } -# Return 1 if the target supports executing MIPS MSA instructions, 0 -# otherwise. Cache the result. - -proc check_mips_msa_hw_available { } { - return [check_cached_effective_target mips_msa_hw_available { - # If this is not the right target then we can skip the test. - if { !([istarget mips*-*-*]) } { - expr 0 - } else { - check_runtime_nocache mips_msa_hw_available { - #if !defined(__mips_msa) - #error "MSA NOT AVAIL" - #else - #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2)) - #error "MSA NOT AVAIL FOR ISA REV < 2" - #endif - #if !defined(__mips_hard_float) - #error "MSA HARD_FLOAT REQUIRED" - #endif - #if __mips_fpr != 64 - #error "MSA 64-bit FPR REQUIRED" - #endif - #include - - int main() - { - v8i16 v = __builtin_msa_ldi_h (0); - v[0] = 0; - return v[0]; - } - #endif - } "-mmsa" - } - }] -} - # Return 1 if the target supports executing SSE2 instructions, 0 # otherwise. Cache the result. @@ -1779,9 +1679,10 @@ proc check_sse2_hw_available { } { int main () { unsigned int eax, ebx, ecx, edx; - if (__get_cpuid (1, &eax, &ebx, &ecx, &edx)) - return !(edx & bit_SSE2); - return 1; + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 1; + + return !(edx & bit_SSE2); } } "" } @@ -1802,9 +1703,10 @@ proc check_sse4_hw_available { } { int main () { unsigned int eax, ebx, ecx, edx; - if (__get_cpuid (1, &eax, &ebx, &ecx, &edx)) - return !(ecx & bit_SSE4_2); - return 1; + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 1; + + return !(ecx & bit_SSE4_2); } } "" } @@ -1825,10 +1727,11 @@ proc check_avx_hw_available { } { int main () { unsigned int eax, ebx, ecx, edx; - if (__get_cpuid (1, &eax, &ebx, &ecx, &edx)) - return ((ecx & (bit_AVX | bit_OSXSAVE)) - != (bit_AVX | bit_OSXSAVE)); - return 1; + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 1; + + return ((ecx & (bit_AVX | bit_OSXSAVE)) + != (bit_AVX | bit_OSXSAVE)); } } "" } @@ -1850,16 +1753,18 @@ proc check_avx2_hw_available { } { int main () { unsigned int eax, ebx, ecx, edx; - if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx) - || ((ecx & bit_OSXSAVE) != bit_OSXSAVE)) - return 1; if (__get_cpuid_max (0, NULL) < 7) return 1; + __cpuid (1, eax, ebx, ecx, edx); + + if (!(ecx & bit_OSXSAVE)) + return 1; + __cpuid_count (7, 0, eax, ebx, ecx, edx); - return (ebx & bit_AVX2) != bit_AVX2; + return !(ebx & bit_AVX2); } } "" } @@ -1881,13 +1786,15 @@ proc check_avx512f_hw_available { } { int main () { unsigned int eax, ebx, ecx, edx; - if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx) - || !(ecx & bit_OSXSAVE)) - return 1; if (__get_cpuid_max (0, NULL) < 7) return 1; + __cpuid (1, eax, ebx, ecx, edx); + + if (!(ecx & bit_OSXSAVE)) + return 1; + __cpuid_count (7, 0, eax, ebx, ecx, edx); return !(ebx & bit_AVX512F); @@ -1930,37 +1837,6 @@ proc check_effective_target_sse4_runtime { } { return 0 } -# Return 1 if the target supports running MIPS Paired-Single -# executables, 0 otherwise. - -proc check_effective_target_mpaired_single_runtime { } { - if { [check_effective_target_mpaired_single] - && [check_mpaired_single_hw_available] } { - return 1 - } - return 0 -} - -# Return 1 if the target supports running Loongson executables, 0 otherwise. - -proc check_effective_target_mips_loongson_runtime { } { - if { [check_effective_target_mips_loongson] - && [check_mips_loongson_hw_available] } { - return 1 - } - return 0 -} - -# Return 1 if the target supports running MIPS MSA executables, 0 otherwise. - -proc check_effective_target_mips_msa_runtime { } { - if { [check_effective_target_mips_msa] - && [check_mips_msa_hw_available] } { - return 1 - } - return 0 -} - # Return 1 if the target supports running AVX executables, 0 otherwise. proc check_effective_target_avx_runtime { } { @@ -1994,6 +1870,114 @@ proc check_effective_target_avx512f_runtime { } { return 0 } +# Return 1 if the target supports executing MIPS Paired-Single instructions, +# 0 otherwise. Cache the result. + +proc check_mpaired_single_hw_available { } { + return [check_cached_effective_target mpaired_single_hw_available { + # If this is not the right target then we can skip the test. + if { !([istarget mips*-*-*]) } { + expr 0 + } else { + check_runtime_nocache mpaired_single_hw_available { + int main() + { + asm volatile ("pll.ps $f2,$f4,$f6"); + return 0; + } + } "" + } + }] +} + +# Return 1 if the target supports executing Loongson vector instructions, +# 0 otherwise. Cache the result. + +proc check_mips_loongson_hw_available { } { + return [check_cached_effective_target mips_loongson_hw_available { + # If this is not the right target then we can skip the test. + if { !([istarget mips*-*-*]) } { + expr 0 + } else { + check_runtime_nocache mips_loongson_hw_available { + #include + int main() + { + asm volatile ("paddw $f2,$f4,$f6"); + return 0; + } + } "" + } + }] +} + +# Return 1 if the target supports executing MIPS MSA instructions, 0 +# otherwise. Cache the result. + +proc check_mips_msa_hw_available { } { + return [check_cached_effective_target mips_msa_hw_available { + # If this is not the right target then we can skip the test. + if { !([istarget mips*-*-*]) } { + expr 0 + } else { + check_runtime_nocache mips_msa_hw_available { + #if !defined(__mips_msa) + #error "MSA NOT AVAIL" + #else + #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2)) + #error "MSA NOT AVAIL FOR ISA REV < 2" + #endif + #if !defined(__mips_hard_float) + #error "MSA HARD_FLOAT REQUIRED" + #endif + #if __mips_fpr != 64 + #error "MSA 64-bit FPR REQUIRED" + #endif + #include + + int main() + { + v8i16 v = __builtin_msa_ldi_h (0); + v[0] = 0; + return v[0]; + } + #endif + } "-mmsa" + } + }] +} + +# Return 1 if the target supports running MIPS Paired-Single +# executables, 0 otherwise. + +proc check_effective_target_mpaired_single_runtime { } { + if { [check_effective_target_mpaired_single] + && [check_mpaired_single_hw_available] } { + return 1 + } + return 0 +} + +# Return 1 if the target supports running Loongson executables, 0 otherwise. + +proc check_effective_target_mips_loongson_runtime { } { + if { [check_effective_target_mips_loongson] + && [check_mips_loongson_hw_available] } { + return 1 + } + return 0 +} + +# Return 1 if the target supports running MIPS MSA executables, 0 otherwise. + +proc check_effective_target_mips_msa_runtime { } { + if { [check_effective_target_mips_msa] + && [check_mips_msa_hw_available] } { + return 1 + } + return 0 +} + # Return 1 if we are compiling for 64-bit PowerPC but we do not use direct # move instructions for moves from GPR to FPR. @@ -2038,6 +2022,30 @@ proc check_ppc_cpu_supports_hw_available { } { }] } +# Return 1 if the target supports executing 750CL paired-single instructions, 0 +# otherwise. Cache the result. + +proc check_750cl_hw_available { } { + return [check_cached_effective_target 750cl_hw_available { + # If this is not the right target then we can skip the test. + if { ![istarget powerpc-*paired*] } { + expr 0 + } else { + check_runtime_nocache 750cl_hw_available { + int main() + { + #ifdef __MACH__ + asm volatile ("ps_mul v0,v0,v0"); + #else + asm volatile ("ps_mul 0,0,0"); + #endif + return 0; + } + } "-mpaired" + } + }] +} + # Return 1 if the target supports executing power8 vector instructions, 0 # otherwise. Cache the result. -- 2.30.2