From 10c2e8ae9ae3f8f41f88fce7de4c2946d23a98fc Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sat, 7 Jan 2012 07:38:53 -0600 Subject: [PATCH] Ruby Cache: Add param for marking caches as instruction only --- configs/ruby/MOESI_hammer.py | 3 ++- src/mem/ruby/system/Cache.py | 1 + src/mem/ruby/system/CacheMemory.cc | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py index fb755ba55..4cc377ec8 100644 --- a/configs/ruby/MOESI_hammer.py +++ b/configs/ruby/MOESI_hammer.py @@ -88,7 +88,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system): # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, - start_index_bit = block_size_bits) + start_index_bit = block_size_bits, + is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py index ab3ec4b29..79ab9b070 100644 --- a/src/mem/ruby/system/Cache.py +++ b/src/mem/ruby/system/Cache.py @@ -39,3 +39,4 @@ class RubyCache(SimObject): assoc = Param.Int(""); replacement_policy = Param.String("PSEUDO_LRU", ""); start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line"); + is_icache = Param.Bool(False, "is instruction only cache"); diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index fbf303ed8..1564128d3 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -55,6 +55,7 @@ CacheMemory::CacheMemory(const Params *p) m_policy = p->replacement_policy; m_profiler_ptr = new CacheProfiler(name()); m_start_index_bit = p->start_index_bit; + m_is_instruction_only_cache = p->is_icache; } void -- 2.30.2