From 10da54f394a4ee1e62de8abd931c3e6240000ef8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 5 Jul 2021 20:01:18 +0100 Subject: [PATCH] debug of SVP64 REMAP --- src/openpower/decoder/isa/caller.py | 18 ++++++++++-------- src/openpower/decoder/isa/svshape.py | 4 +++- .../decoder/isa/test_caller_svp64_matrix.py | 5 ++++- 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index d327d05a..a73085cf 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1199,7 +1199,7 @@ class ISACaller: # for when SVSHAPE is active, a very bad hack here (to be replaced) # using pre-arranged schedule. all of this is awful but it is a # start. next job will be to put the proper activation in place - yield self.dec2.remap_active.eq(self.last_op_svshape) + yield self.dec2.remap_active.eq(1 if self.last_op_svshape else 0) if self.last_op_svshape: # get four SVSHAPEs. here we are hard-coding # SVSHAPE0 to FRT, SVSHAPE1 to FRA, SVSHAPE2 to FRC and @@ -1217,24 +1217,26 @@ class ISACaller: SVSHAPE2.get_iterator(), SVSHAPE3.get_iterator(), ] + rremaps = [] for i, remap in enumerate(remaps): # XXX hardcoded! pick dststep for out (i==0) else srcstep step = dststep if (i == 0) else srcstep # this is terrible. O(N^2) looking for the match. but hey. - print ("remap", i, step) for idx, remap_idx in enumerate(remap): if idx == step: break if i == 0: - yield self.dec2.o_step.eq(step) - yield self.dec2.o2_step.eq(step) + yield self.dec2.o_step.eq(remap_idx) + yield self.dec2.o2_step.eq(remap_idx) elif i == 1: - yield self.dec2.in1_step.eq(step) + yield self.dec2.in1_step.eq(remap_idx) elif i == 2: - yield self.dec2.in2_step.eq(step) + yield self.dec2.in2_step.eq(remap_idx) elif i == 3: - yield self.dec2.in3_step.eq(step) - print ("\t", idx, remap_idx) + yield self.dec2.in3_step.eq(remap_idx) + rremaps.append((i, idx, remap_idx)) + for x in rremaps: + print ("shape remap", x) # after that, settle down (combinatorial) to let Vector reg numbers # work themselves out yield Settle() diff --git a/src/openpower/decoder/isa/svshape.py b/src/openpower/decoder/isa/svshape.py index 8b133935..8ab51c20 100644 --- a/src/openpower/decoder/isa/svshape.py +++ b/src/openpower/decoder/isa/svshape.py @@ -12,7 +12,9 @@ class SVSHAPE(SelectableInt): offs = 0 # set up sub-fields from Record layout self.fsi = {} - for field, width in SVP64REMAP.layout: + l = deepcopy(SVP64REMAP.layout) + l.reverse() + for field, width in l: v = FieldSelectableInt(self, tuple(range(offs, offs+width))) self.fsi[field] = v offs += width diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 6e86d168..28d42cac 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -58,7 +58,7 @@ class DecoderTestCase(FHDLTestCase): print ("\t", yf) # and create a linear result2, same scheme - #result2 = [0] * (ydim1*xdim2) + #result1 = [0] * (ydim1*xdim2) res = [] @@ -83,6 +83,9 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, svstate=svstate, initial_fprs=fprs) print ("spr svshape0", sim.spr['SVSHAPE0']) + print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) print ("spr svshape1", sim.spr['SVSHAPE1']) print ("spr svshape2", sim.spr['SVSHAPE2']) print ("spr svshape3", sim.spr['SVSHAPE3']) -- 2.30.2