From 111434f61a1c907b6a25dbc132ba59a9369ad8d0 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 22 May 2016 02:35:33 -0700 Subject: [PATCH] Allow delegation of device interrupts --- riscv/encoding.h | 9 ++++++--- riscv/processor.cc | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 5405148..bdba5f2 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -39,6 +39,9 @@ #define MIP_STIP (1 << IRQ_S_TIMER) #define MIP_HTIP (1 << IRQ_H_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP @@ -61,9 +64,9 @@ #define IRQ_S_TIMER 5 #define IRQ_H_TIMER 6 #define IRQ_M_TIMER 7 -#define IRQ_S_DEV 9 -#define IRQ_H_DEV 10 -#define IRQ_M_DEV 11 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 #define IRQ_COP 12 #define IRQ_HOST 13 diff --git a/riscv/processor.cc b/riscv/processor.cc index ada5cd7..63339b1 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -254,7 +254,7 @@ static bool validate_vm(int max_xlen, reg_t vm) void processor_t::set_csr(int which, reg_t val) { val = zext_xlen(val); - reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_COP); + reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP); reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; switch (which) { -- 2.30.2